Core Version | Vivado Tools Version |
---|---|
v2.0(Rev. 6) | 2014.4 |
v2.0(Rev. 5) | 2014.3 |
v2.0(Rev. 5) | 2014.2 |
v2.0(Rev. 4) | 2014.1 |
v2.0(Rev. 3) | 2013.4 |
v2.0(Rev. 2) | 2013.3 |
v2.0(Rev. 1) | 2013.2 |
v2.0 | 2013.1 |
Answer Record | Title |
---|---|
N/A | N/A |
Answer Record | Title | Version Found | Version Resolved |
---|---|---|---|
(Xilinx Answer 63525) | The overflow flag is not asserted when it occurs | v2.0(Rev. 6) | N/A |
(Xilinx Answer 61375) | The IP outputs incorrect results when running behavioral simulation with VCS-MX I-2014.03 or VCS-MX I-2014.03-2. | v2.0(Rev.5) | N/A |
(Xilinx Answer 55109) | Why is there a mismatch between C model and HDL on the overflow output when using the Pipelined, Streaming I/O architecture with user-defined scaling? | v1.0 | N/A |
(Xilinx Answer 53465) | 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with Error: Failed to find design work <Core name>? | v1.0 | v2.0 |
AR# 54482 | |
---|---|
日期 | 03/23/2015 |
状态 | Active |
Type | 版本说明 |
Tools | |
IP |