This answer record contains the Release Notes and Known Issues for the LogiCORE IP 3GPP LTE PUCCH Receiver core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP 3GPP LTE PUCCH Receiver core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-pucch-rec-lte.html
General Information
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v2.0 (Rev. 4) | 2014.1 |
| v2.0 (Rev. 3) | 2013.4 |
| v2.0 (Rev. 2) | 2013.3 |
| v2.0 (Rev. 1) | 2013.2 |
| v2.0 | 2013.1 |
General Guidance
The table below provides answer records for general guidance when using the LogiCORE IP 3GPP LTE PUCCH Receiver core.
| Answer Record | Title |
|---|---|
| N/A | N/A |
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP 3GPP LTE PUCCH Receiver core, starting with v2.0, initially released in Vivado Design Suite 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 60620) | LogiCore IP 3GPP LTE PUCCH Receiver v2.0(Rev.4) - the core may fail to meet timing when it is generated out-of-context |
v2.0 (Rev.4) | N/A |
| (Xilinx Answer 54638) | Why does the 3GPP LTE PUCCH Receiver fail to meet timing? | v2.0 (Rev. 4) | N/A |
| (Xilinx Answer 57990) | LogiCORE IP LTE PUCCH Receiver v2.0(Rev.2) - Why does the core output incorrect data with 2013.3 Vivado Simulator? | v2.0 (Rev. 2) | N/A |
| (Xilinx Answer 53645) | 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with Error: Failed to find design work <Core name>? |
v1.0 | v2.0 |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 57990 | LogiCORE IP LTE PUCCH Receiver v2.0(Rev.2) - Why does the core output incorrect data with 2013.3 Vivado Simulator? | N/A | N/A |
| 60620 | LogiCORE IP 3GPP LTE PUCCH Receiver v2.0(Rev.4) - The core may fail to meet timing when it is generated out-of-context | N/A | N/A |
| AR# 54483 | |
|---|---|
| 日期 | 11/10/2014 |
| 状态 | Active |
| Type | 版本说明 |
| Tools |
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| IP |
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