This answer record contains the Release Notes and Known Issues for the LogiCORE IP Peak Cancellation Crest Factor Reduction (PC CFR) core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP Peak Cancellation Crest Factor Reduction (PC CFR) core IP Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
The table below provides answer records for general guidance when using the LogiCORE IP Peak Cancellation Crest Factor Reduction (PC CFR) core.
|(Xilinx Answer 38331)||Is there a formula to calculate the Allocator Spacing subject to the distance and number of carriers?|
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Peak Cancellation Crest Factor Reduction (PC CFR) core, starting with v4.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 53465)||2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with Error: Failed
to find design work <Core name>?
|(Xilinx Answer 55110)||pc_cfr v3.1 is failing VHDL & Verilog testbench XSIM simulation: "FATAL_ERROR: File registers.txt could not be opened"||v3.1||v4.0|