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AR# 54516

LogiCORE IP Asynchronous Sample Rate Converter (ASRC) - Release Notes and Known Issues for Vivado 2013.1 and newer tools versions


This answer record contains the Release Notes and Known Issues for the LogiCORE IP Asynchronous Sample Rate Converter (ASRC) core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
For past known issue logs and ISE support information, see the IP Release Notes Guide (XTP025):

LogiCORE IP Asynchronous Sample Rate Converter (ASRC) core IP Page:

NOTE: Not recommended for new designs.  The core is removed from the IP catalog as of 2014.3.

Users who need an Asynchronous Sample Rate Converter can request an unsupported copy of the source code for the Asynchronous Sample Rate Converter from the Asynchronous Sample Rate Converter lounge.


General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

Vivado Tools
v2.0 (Rev. 3) 2014.1
v2.0 (Rev. 2) 2013.3
v2.0 (Rev. 1) 2013.2
v2.0 2013.1

Table 2 provides answer records for general guidance when using the LogiCORE IP Asynchronous Sample Rate Converter (ASRC) core.

Table 2: General Guidance

Answer Record Title
(Xilinx Answer 50170) Why do I see variation or "glitches" on the output when my input is a DC value?
(Xilinx Answer 52645) Does clock jitter affect the ASRC results and can it cause THD glitches?
(Xilinx Answer 52889) Why do I see jitter when the input and output are the same sample rate using the automatic mode, but not for manual mode?

Known and Resolved Issues

The following table provides known issues for the LogiCORE IP Asynchronous Sample Rate Converter (ASRC) core, starting with v2.0, initially released in Vivado Design Suite 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version

Revision History

10/23/2013 - Added v2.0 (Rev. 1) and v2.0 (Rev. 2) to Version Table
04/03/2013 - Initial release



Answer Number 问答标题 问题版本 已解决问题的版本
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A


AR# 54516
日期 11/18/2014
状态 Active
Type 版本说明
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.3
  • Asynchronous Sample Rate Converter (ASRC)