This answer record contains the Release Notes and Known Issues for the AXI4-Stream to Video Out LogiCORE IP and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
For past known issue logs and ISE support information, see the IP Release Notes Guide (XTP025):
AXI4-Stream to Video Out LogiCORE IP Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|Vivado Tools |
|v4.0(Rev. 10)||2018.3||(Xilinx Answer 71806)|
|v4.0(Rev. 9)||2018.2||(Xilinx Answer 71212)|
|v3.0 (Rev. 7)||2015.1|
|v3.0 (Rev. 6)||2014.4|
|v3.0 (Rev. 5)||2014.3|
|v3.0 (Rev. 4)||2014.1|
|v3.0 (Rev. 3)||2013.4|
|v3.0 (Rev. 2)||2013.3|
|v3.0 (Rev. 1)||2013.2|
Table 2 provides answer records for general guidance when using the AXI4-Stream to Video Out LogiCORE IP.
Table 2: General Guidance
|(Xilinx Answer 58410)||Why is there no output from the AXI4-Stream to Video Out core?|
Known and Resolved Issues
The following table provides known issues for the AXI4-Stream to Video Out LogiCORE IP core, starting with v3.0, initially released in Vivado 2013.1 design tools.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version |
|(Xilinx Answer 61430)||Why does the AXI4-Stream to Video Out core fail to lock, when the TVALID is deasserted ('0') before TLAST is asserted ('1')?||v3.0|
|(Xilinx Answer 53882)||Why do I have a Video Format option for Bayer Sensor and Luma Only?||v1.0||v3.0|
|(Xilinx Answer 56274)||Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?||v3.0||v3.0 (Rev. 2)|
Please seek technical support via the Video Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx User Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
|01/4/2019||Added v4.0 Rev versions up to 2018.3 to Version Table|
|10/29/2015||Added v4.0, v3.0 (Rev. 7), v3.0 (Rev. 6), and v3.0 (Rev. 5) to Version Table|
|07/31/2014||Added (Xilinx Answer 58410)|
|07/09/2014||Added v3.0 (Rev. 3) and v3.0 (Rev. 4) to Version Table, (Xilinx Answer 61430).|
|10/23/2013||Added v3.0 (Rev. 2) to Version Table and updated Known and Resolved Issues table for 2013.3.|
|06/19/2013||Added v3.0 (Rev. 1) to Version Table, (Xilinx Answer 56274)|