We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54518

LogiCORE IP Chroma Resampler - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the LogiCORE IP Chroma Resampler core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
For past known issue logs and ISE support information, see the IP Release Notes Guide (XTP025):

LogiCORE IP Chroma Resampler core IP Page:


General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version
Vivado Tools
v4.0 (Rev. 2) 2013.3
v4.0 (Rev. 1) 2013.2
v4.0 2013.1

Table 2 provides answer records for general guidance when using the LogiCORE IP Chroma Resampler core.

Table 2: General Guidance

Answer Record Title

Known and Resolved Issues

The following table provides known issues for the LogiCORE IP Chroma Resampler core, starting with v4.0, initially released in Vivado 2013.1 design tools.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version
(Xilinx Answer 57773) Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation? v3.01.a N/A
(Xilinx Answer 52215) Why does my core fail timing with a Critical Warning? v3.01.a v4.0 (Rev. 2)
(Xilinx Answer 56274) Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design? v4.0 v4.0 (Rev. 2)
(Xilinx Answer 55980) Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? v4.0 v4.0 (Rev. 1)

Revision History

10/23/2013 - Added v4.0 (Rev. 2) Version Table,(Xilinx Answer 57773) and updated Known and Resolved Issues table for 2013.3.
06/19/2013 - Added v4.0 (Rev. 1) to Version Table, (Xilinx Answer 56274), (Xilinx Answer 55980)
04/03/2013 - Initial release



Answer Number 问答标题 问题版本 已解决问题的版本
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A



Answer Number 问答标题 问题版本 已解决问题的版本
44487 LogiCORE IP Chroma Resampler - Release Notes and Known Issues N/A N/A
61625 Video IP Example Design Landing Page N/A N/A
AR# 54518
日期 11/10/2014
状态 Active
Type 版本说明
  • Vivado Design Suite - 2013.1
  • Chroma Resampler