This answer record contains the Release Notes and Known Issues for the SMPTE SD/HD/3G-SDI (SMPTE SDI) core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
SMPTE SD/HD/3G-SDI LogiCORE IP Page:
https://www.xilinx.com/content/xilinx/en/products/intellectual-property/smpte_sdi.html
**This core is now in maintenance mode and it is suggested to update to the newer UHD-SDI solution if starting a new project**
See (PG289) and (PG290) for more information on the newer subsystem cores.
General Information
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v3.0 (Rev. 8) | 2016.3 |
| v3.0 (Rev. 7) | 2016.1 |
| v3.0 (Rev. 6) | 2015.3 |
| v3.0 (Rev. 5) | 2015.2 |
| v3.0 (Rev. 4) | 2015.1 |
| v3.0 (Rev. 3) | 2014.4 |
| v3.0 (Rev. 2) | 2014.3 |
| v3.0 (Rev. 1) | 2014.1 |
| v3.0 | 2013.3 |
| v2.0 (Rev. 1) | 2013.2 |
| v2.0 | 2013.1 |
General Guidance
The table below provides answer records for general guidance when using the LogiCORE IP SMPTE SD/HD/3G-SDI core.
| Answer Record | Title |
|---|---|
| (Xilinx Answer 70041) | IP Latency Information SMPTE SDI IP in 3G-SDI mode |
| (Xilinx Answer 65953) | How do I map RGB data to the SMPTE SD/HD/3G-SDI Core? |
| (Xilinx Answer 64273) | Does the IP support the Synchronous Switching feature of the SMPTE-SDI standard? |
| (Xilinx Answer 62645) | Can non-standard resolutions be supported? |
| (Xilinx Answer 59903) | How do I capture the Field ID from an in SDI RX when the input is interlaced? |
| (Xilinx Answer 59601) | Does the SMPTE SD/HD/3G-SDI IP support Artix-7 -1 speed grade? |
| (Xilinx Answer 51092) | How do I connect up the SMPTE SD/HD/3G-SDI core to the High Speed SERDES on my device? |
| (Xilinx Answer 51114) | Does the SMPTE SD/HD/3G-SDI IP support the GTX High Speed SERDES on Kintex-7 ES devices? |
| (Xilinx Answer 53522) | How many cycles does the crc_err_a and crc_err_b remain asserted? |
| (Xilinx Answer 54366) | Is the value mentioned in the Table 9 of XAPP592 and XAPP892 the frame rate? |
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP SMPTE SD/HD/3G-SDI core, starting with v2.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 67907) | XAPP1290 (v1.0) - Why am I not able to properly generate a 3G-SDI Level B output? | v3.0 | N/A |
| (Xilinx Answer 67629) | When using the XAPP1290 reference design, I cannot see the Color Bar when using CPLL? | v3.0 | N/A |
| (Xilinx Answer 61612) | When using XAPP592 v2.0, why does the SMPTE 352 payload ID capture module in the SMPTE SDI receiver core lock up when the GTX RX changes line rates? | v3.0 | XAPP592 v2.1 |
| (Xilinx Answer 61474) | Why does the SMPTE SDI core stop working when using the 7 Series FGPAs Transceiver Wizard v3.3 with the XAPP592 v2.0 code? | v3.0 | XAPP592 v2.0 |
| (Xilinx Answer 60303) | When targeting Artix-7 and using XAPP1097 v1.0, why do I see intermittent failures, or failure to lock when changing SDI standards? | v3.0 | XAPP1097 v1.1 |
Revision History
| 01/04/2021 | added note for the UHD-SDI subsystem Product Guides |
| 10/28/2016 | Added (Xilinx Answer 70041) |
| 10/28/2016 | Added v3.0 (Rev. 8) to Version Table and (Xilinx Answer 67907) |
| 08/02/2016 | Added (Xilinx Answer 67629) |
| 05/09/2016 | Added (Xilinx Answer 65953) |
| 04/06/2016 | Added v3.0 (Rev. 5), Added v3.0 (Rev. 5) and v3.0 (Rev. 7) to Version Table |
| 04/01/2015 | Added v3.0 (Rev. 3) and v3.0 (Rev. 4) to Version Table and (Xilinx Answer 64273) |
| 10/29/2014 | Added v3.0 (Rev. 1) and v3.0 (Rev. 2) to Version Table and (Xilinx Answer 62645) |
| 09/15/2014 | Added (Xilinx Answer 59903) |
| 08/01/2014 | Added (Xilinx Answer 61612), (Xilinx Answer 61474), (Xilinx Answer 61612) |
| 05/29/2014 | Added (Xilinx Answer 60303) |
| 03/03/2014 | Added (Xilinx Answer 59601) |
| 10/23/2013 | Added v2.0 (Rev. 1) and v3.0 to Version Table |
| 04/03/2013 | Initial release |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 56852 | Xilinx Multimedia, Video and Imaging Solution Center - Top Issues | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 50905 | LogiCORE IP SMPTE SDI (SD/HD/3G-SDI) - Release Notes and Known Issues | N/A | N/A |
| 61625 | Video IP Example Design Landing Page | N/A | N/A |
| AR# 54531 | |
|---|---|
| 日期 | 01/11/2021 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |
| IP | |