This answer record contains the Release Notes and Known Issues for the LogiCORE IP SMPTE2022-5/6 Video over IP Transmitter core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP SMPTE2022-5/6 Video over IP Transmitter core IP Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|v3.0 (Rev. 4)||2014.1|
|v3.0 (Rev. 3)||2013.4|
|v3.0 (Rev. 2)||2013.3|
|v3.0 (Rev. 1)||2013.2|
The table below provides answer records for general guidance when using the LogiCORE IP SMPTE2022-5/6 Video over IP Transmitter core.
|(Xilinx Answer 62090)||How do I use two Ethernet Cores that have different reference clocks, when there is only one Ethernet clock input?|
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP SMPTE2022-5/6 Video over IP Transmitter core, starting with v3.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 63642)||Why is the FRCount not transmitted for SD-SDI?||v4.0 (Rev. 1)||v4.0 (Rev. 2)|
|(Xilinx Answer 63260)||Why does the SMPTE2022-5/6 TX sometimes ignore the non-block aligned configuration register?||v4.0 (Rev. 1)||v4.0 (Rev. 2)|
|(Xilinx Answer 63005)||Why do I see wrong RTP timestamps, which cause a rapid packet buffer decay at my SMPTE2022-5/6 Video Over IP Receiver?||v4.0 (Rev. 1)||v4.0 (Rev. 2)|
|(Xilinx Answer 62904)||Why do I see the TLL and TOS values in the registers different between the primary and secondary links?||v4.0 (Rev. 1)||v4.0 (Rev.2)|
|(Xilinx Answer 62520)||Why is the Primary MAC address stuck at 0?||v4.0||v4.0 (Rev. 1)|
|04/05/2017||Added v4.0 (Rev.7), v4.0 (Rev. 8), v4.0 (Rev. 9), and v4.0 (Rev. 10) to Version Table|
|04/22/2016||Added v4.0 (Rev.2), v4.0 (Rev. 3), v4.0 (Rev. 4), v4.0 (Rev. 5) and v4.0 (Rev. 6) to Version Table|
|02/19/2015||Added (Xilinx Answer 63642)|
|01/08/2015||Added (Xilinx Answer 62904), (Xilinx Answer 63005) and (Xilinx Answer 63260)|
|10/20/2014||Added (Xilinx Answer 62520)|
|10/08/2014||Added v3.0 (Rev.3), v3.0 (Rev. 4) and v4.0 to Version Table and (Xilinx Answer 62090)|
|10/23/2013||Added v3.0 (Rev. 1) and v3.0 (Rev. 2) to Version Table|