This answer record contains the Release Notes and Known Issues for the LogiCORE IP Video Deinterlacer core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
Video Deinterlacer LogiCORE IP Page:
The Video Deinterlacer is no longer being updated.
Users are recommended to use the Video Processing Subsystem's Deinterlacer configuration, (Xilinx Answer 65449).
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|v4.0 (Rev. 12)||2017.3|
|v4.0 (Rev. 11)||2016.3|
|v4.0 (Rev. 10)||2016.1|
|v4.0 (Rev. 9)||2015.3|
|v4.0 (Rev. 8)||2015.1|
|v4.0 (Rev. 7)||2014.4|
|v4.0 (Rev. 6)||2014.3|
|v4.0 (Rev. 5)||2014.2|
|v4.0 (Rev. 4)||2014.1|
|v4.0 (Rev. 3)||2013.4|
|v4.0 (Rev. 2)||2013.3|
|v4.0 (Rev. 1)||2013.2|
The table below provides answer records for general guidance when using the LogiCORE IP Video Deinterlacer core.
|(Xilinx Answer 51338)||Design Advisory Master Answer Record for LogiCORE IP Video Deinterlacer|
|(Xilinx Answer 59850)||Does the Video Deinterlacer expect an Start of Frame (SOF) for each field or each frame?|
|(Xilinx Answer 59848)||Does the Video Deinterlacer support odd integers for the frame height?|
|(Xilinx Answer 59461)||Why does the Video Deinterlacer hang sometimes, when the video input is interrupted?|
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Video Deinterlacer core, starting with v4.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 67581)||Why does the provided demo_tb simulation fail to generate any output?||v4.0 (Rev. 9)||N/A|
|(Xilinx Answer 66708)||Problems when upgrading IP to v5.0||v4.0||N/A|
|(Xilinx Answer 61833)||Why does the Accept Video bit in the Control Register always read back as '0'?||v3.00.a||v4.0|
|(Xilinx Answer 60171)||Why does changing the base and high address in the configuration GUI have no affect on the Video Deinterlacer core?||v3.00.a||N/A|
|(Xilinx Answer 59127)||The Pulldown 2:2 Field mode selection description is reversed||v2.00.a||PG017 2014.1|
|(Xilinx Answer 56274)||Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?||v4.0 (Rev. 2)||v4.0 (Rev. 2)|
|(Xilinx Answer 56277)||Why does the s_axis_video_tready signal behavior appear incorrect for the first input frame?||v3.00.a||N/A|
|(Xilinx Answer 50586)||Why do I always get zeros back when reading from the Video Deinterlacer registers?||v2.00.a||v4.0|
Users are recommended to use the Video Processing Subsystem's Deinterlacer Scaler configuration, (Xilinx Answer 65449).
|04/04/2018||Added v4.0 (Rev. 10), v4.0 (Rev. 11) and v4.0 (Rev. 12) to Version Table, added (Xilinx Answer 67581)|
|03/07/2016||Added v4.0 (Rev. 6), v4.0 (Rev. 7), v4.0 (Rev. 8), and v4.0 (Rev. 9) to Version Table, added (Xilinx Answer 66708)|
|08/25/2014||Added v4.0 (Rev. 5) to Version Table, added (Xilinx Answer 61833)|
|04/16/2014||Added v4.0 (Rev. 3) and v4.0 (Rev. 4) to Version Table, added (Xilinx Answer 60171)|
|03/19/2014||Added (Xilinx Answer 59848), (Xilinx Answer 59850)|
|02/18/2014||Added (Xilinx Answer 59461)|
|01/15/2014||Added (Xilinx Answer 59127)|
|10/23/2013||Added v4.0 (Rev. 2) to Version Table, updated Known and Resolved Issues table for 2013.3.|
|06/19/2013||Added v4.0 (Rev. 1) to Version Table, added (Xilinx Answer 56274)|
|06/06/2013||Added (Xilinx Answer 56277)|