This answer record contains the Release Notes and Known Issues for the LogiCORE IP Video Timing Controller core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
For past known issue logs and ISE support information, see the IP Release Notes Guide (XTP025):
LogiCORE IP Video Timing Controller Core Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|Vivado Tools |
|v6.1 (Rev. 10)||2016.4|
|v6.1 (Rev. 9)||2016.3|
|v6.1 (Rev. 8)||2016.2|
|v6.1 (Rev. 7)||2016.1|
|v6.1 (Rev. 6)||2015.3|
|v6.1 (Rev. 5)||2015.1|
|v6.1 (Rev. 4)||2014.4|
|v6.1 (Rev. 3)||2014.3|
|v6.1 (Rev. 2)||2014.2|
|v6.1 (Rev. 1)||2014.1|
|v6.0 (Rev. 2)||2013.3|
|v6.0 (Rev. 1)||2013.2|
Table 2 provides answer records for general guidance when using the LogiCORE IP Video Timing Controller core.
Table 2: General Guidance
|(Xilinx Answer 65801)||Using the VTC with the AXI Stream to Video Out for interlaced format detection|
|(Xilinx Answer 39413)||What signals are needed for the timing to be correctly detected and regenerated?|
|(Xilinx Answer 47158)||Why do I not see blanking signals generated when I select the blanking signal detection?|
|(Xilinx Answer 55248)||Why do I get the following CRITICAL WARNING: [Vivado 12-259] No clocks specified, please specify clocks, for my IP, or why do I get CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_max_delay?|
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Video Timing Controller core, starting with v6.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version |
|(Xilinx Answer 69227)||How do I configure the Video Timing Controller to de-assert VBLANK as the same time as the HBLANK at the end of the last line of the frame?||v 6.1||N/A|
|(Xilinx Answer 68711)||Why do I not see any VSYNC or VBLANK outputs when using constant mode with CUSTOM timing?||v6.1 (Rev. 10)||N/A|
|(Xilinx Answer 63700)||Driver does not set 'Interlaced' bit in Generator Encoding Register||v6.1||N/A|
|(Xilinx Answer 61228)||field_id_out does not toggle in constant mode||v6.0||N/A|
|(Xilinx Answer 61684)||Why does the VTC lock signal remain asserted when the video clock is removed?||v6.0||N/A|
|(Xilinx Answer 56274)||Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?||v6.0||v6.0 (Rev. 2)|
|(Xilinx Answer 56271)||Why do I get a CRITICAL WARNING: [Common 17-161] Invalid option value '6.73400 6.73400' specified for 'delay' in Vivado 2013.1 or 2013.2, my clock source is from a clock mux?||v6.0||v6.0 (Rev. 2)|
|(Xilinx Answer 52215)||Why does my core fail timing with a Critical Warning?||v5.01.a||v6.0 (Rev. 2)|
|(Xilinx Answer 54660)||When using the Video Timing Controller, Test Pattern Generator, RGB2YCrCb Color-Space Converter or YCrCb2RGB Color-Space Converter cores, why do I get an error saying that my design can not generate a bitstream?||v5.01.a||v6.0 (Rev. 2)|
|(Xilinx Answer 54611)||Why does Video Timing Controller Generator reset early in relation to the Blanking Signals, if both the detector and the generator are enabled?||v5.01.a||v6.0|
|(Xilinx Answer 52741)||Why is the VTC Generation always producing 720p output timing signals at startup when the AXI4-Lite interface is used?||v5.01.a||v6.0|
|(Xilinx Answer 52724)||Why does the VTC Generation always wait for the VTC Detection to lock when both the VTC Generation and VTC Detection are enabled?||v5.01.a||v6.0|
|(Xilinx Answer 55980)||Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?||v5.01.a||v6.0 (Rev. 1)|
|05/26/2017||Added (Xilinx Answer 69227)|
|02/07/2017||Added v6.1 (Rev. 7), v6.1 (Rev. 8), v6.1 (Rev. 9), and v6.1 (Rev. 10) to Version Table, (Xilinx Answer 68711)|
|03/13/2015||Added v6.1 (Rev. 3), v6.1 (Rev. 4), v6.1 (Rev. 5), and v6.1 (Rev. 6) to Version Table, (Xilinx Answer 65801)|
|03/13/2015||Added (Xilinx Answer 63700)|
|09/26/2014||Added (Xilinx Answer 61228)|
|08/01/2014||Added v6.0, v6.1 (Rev. 1) and v6.1 (Rev. 2) to Version Table, (Xilinx Answer 61684)|
|10/23/2013||Added v6.0 (Rev. 2) to Version Table (Xilinx Answer 54660) and updated Known and Resolved Issues table for 2013.3.|
|06/19/2013||Added v6.0 (Rev. 1) to Version Table, (Xilinx Answer 56274), (Xilinx Answer 56271)|
|05/17/2013||Added (Xilinx Answer 55980)|