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AR# 54584

MIG 7 Series - Needed XDC constraint changes when using a Synplify netlist within Vivado

Description

Synplify (or other third-party synthesis tools) are not integrated as a part of the Vivado Design Suite. For more information, see (Xilinx Answer 50280). Additionally, MIG 7 Series does not support Synplify synthesis with Vivado implementation. This answer record is intended to help customers that require using Synplify.

When integrating a Synplify generated netlist containing a MIG 7 Series core into Vivado Design Suite, some XDC constraint changes are needed for proper implementation. This answer record details the required changes.

解决方案

MIG 7 Series DDR3/DDR2 SDRAM Solutions

1. MIG generates the following XDC multi-cycle path constraints:
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
                    -to   [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
                    -setup 6

set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
                    -to   [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
                    -hold 5

This path is not valid when using Synplify Pro with Vivado. The valid constraints are as follows:
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r*}] \
                    -to   [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
                    -setup 6

set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r*}] \
                    -to   [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
                    -hold 5

2. MIG generates the following XDC Multi-cycle path constraints for the XADC temperature monitor logic:
set_multicycle_path -to   [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] \
                    -setup 2 -end

set_multicycle_path -to   [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] \
                    -hold 1 end

The valid constraints when using Synplify Pro with Vivado are as follows:
set_multicycle_path -to   [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*rst*}] \
                    -setup 2 -end

set_multicycle_path -to   [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*rst*}] \
                    -hold 1 -end

QDRII+ and RLDRAMII/III Solutions

1. The PHASER_OUT XDC constraints generated by MIG are similar to the following:
set_property LOC PHASER_OUT_PHY_X1Y27 [get_cells  -hier -filter {NAME =~ */qdr_rld_phy_4lanes_2.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_D.qdr_rld_byte_lane_D/PHASER_OUT_inst.phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y26 [get_cells  -hier -filter {NAME =~ */qdr_rld_phy_4lanes_2.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_C.qdr_rld_byte_lane_C/PHASER_OUT_inst.phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y25 [get_cells  -hier -filter {NAME =~ */qdr_rld_phy_4lanes_2.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_B.qdr_rld_byte_lane_B/PHASER_OUT_inst.phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y24 [get_cells  -hier -filter {NAME =~ */qdr_rld_phy_4lanes_2.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_A.qdr_rld_byte_lane_A/PHASER_OUT_inst.phaser_out}]

The valid constraints when using Synplify Pro with Vivado are similar to the following:

set_property LOC PHASER_OUT_PHY_X1Y27 [get_cells  -hier -filter {NAME =~ */qdr_rld_phy_4lanes_2.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_D.qdr_rld_byte_lane_D/genblk*.PHASER_OUT_inst.phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y26 [get_cells  -hier -filter {NAME =~ */qdr_rld_phy_4lanes_2.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_C.qdr_rld_byte_lane_C/genblk*.PHASER_OUT_inst.phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y25 [get_cells  -hier -filter {NAME =~ */qdr_rld_phy_4lanes_2.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_B.qdr_rld_byte_lane_B/genblk*.PHASER_OUT_inst.phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y24 [get_cells  -hier -filter {NAME =~ */qdr_rld_phy_4lanes_2.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_A.qdr_rld_byte_lane_A/genblk*.PHASER_OUT_inst.phaser_out}]

AR# 54584
创建日期 02/26/2013
Last Updated 06/03/2013
状态 Active
Type 综合文章
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series