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AR# 54645

Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

Xilinx PCI Express Cores Page:

http://www.xilinx.com/technology/protocols/pciexpress.htm


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

解决方案

General Information

For release notes on v1.7 of the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core, see (Xilinx Answer 47441).

Supported devices can be found in the following three locations:

Changes in v4.2 (Rev2)


  • Feature Enhancement
    • Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
  • Other
    • Added support for FLG1155/FLG1931 packages for xc7vh580t device, FLG1931 for xc7vh870t device, FFV1156/FFV1761 for xc7vx330t device, FFV1157/FFV1158/FFV1927 for xc7vx415T device
    • Revision change in one or more subcores
Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v4.2 (Rev2)2016.3
v4.2 (Rev1)2016.2
v4.22016.1
v4.1 (Rev1)2015.4
v4.12015.3
v4.0 (Rev1)2015.2
v4.02015.1
v3.0(Rev4)2014.4.1
v3.0 (Rev4)
2014.4
v3.0 (Rev3)2014.3
v3.0 (Rev2)2014.2
v3.0 (Rev1)
2014.1
v3.02013.4
v2.22013.3
v2.12013.2
v2.02013.1
v1.42012.4


Design Advisory

(Xilinx Answer 62296)Design Advisory for 7 Series/Virtex-7 FGPA Gen3 Integrated Block for PCI Express / AXI Bridge for PCI Express (Vivado 2014.1/2014.2/2014.3) - Tool reports 'constant_clock' and 'unconstrained_internal_endpoints' when implementing core configured as Gen1

Tactical Patch

The following table provides a list of tactical patches for the Virtex-7 Gen3 Integrated Block Wrapper for PCI Express core, applicable on corresponding Vivado tool versions.

Answer RecordCore Version (After installing the Patch)Tool Version
(Xilinx Answer 64153)
v3.0 (Rev. 5)
2014.4.1
(Xilinx Answer 67111)v4.2 (Rev. 67111)2016.1

Known and Resolved Issues

The following table provides known issues for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core, starting with v2.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version that the problem was first discovered in.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 65569)Virtex-7 GTH QPLL temperature compensation attribute updatev4.2 (Rev1)
(Xilinx Answer 67111)Issue with MSI-X Table Offset
v4.2v4.2 (Rev1)
(Xilinx Answer 67172)Example Design Simulation with VCS Simulator hangs indefinitelyv2.1Not Resolved Yet
(Xilinx Answer 65500)
Example Design Simulation with VCS Simulator Failsv4.1Not Resolved Yet
(Xilinx Answer 64153)PCIE_ASYNC_EN is not set correctly for Asynchronous Clocking v3.0(Rev4)v4.0 (Rev1)
(Xilinx Answer 62787)Extended Tag Field Support v3.0 (Rev3)NA
(Xilinx Answer 62854)Excessive BUFG usage v3.0 (Rev3)
v3.0(Rev4)
(Xilinx Answer 60022)
TIMING-10#1 Warning Missing property on synchronizerv3.0 (Rev1)v3.0 (Rev2)
(Xilinx Answer 59900)Post Synthesis/Implementation Netlist Functional/Timing Simulation Supportv3.0 (Rev1)v4.0
(Xilinx Answer 59899)Resizable BAR Extended Capability Supportv3.0v3.0 (Rev2)
(Xilinx Answer 59961)PCISIG Compliance Testing v3.0v3.0 (Rev2)
(Xilinx Answer 59988)Out of the box example design simulation fails with 'Address Aligned' mode for 256-bit AXI Interface and 64-bit BAR configuration v3.0v3.0 (Rev2)
(Xilinx Answer 58723)PIPE Simulation does not work with 250 MHz Reference Clockv2.2v3.0(Rev1)
(Xilinx Answer 58271) Legacy Interrupt Mode information in PG023 is not correctv2.2v3.0
(Xilinx Answer 58071)Does not flag fatal error during completion buffer overflowv2.2NA
(Xilinx Answer 56976)PF1_SRIOV_FIRST_VF_OFFSET is incorrectv2.1v3.0(Rev1)
(Xilinx Answer 56975)Field to set "VF Device ID" in PF1 SRIOV Config tab of GUI is grayed outv2.1v2.2
(Xilinx Answer 54902)IES/GES Device Support in Vivado 2013.1 and ISE Design Suite 14.5v2.0N/A
(Xilinx Answer 55309)ERROR:Place:1340 - PAD.pci_exp_rxn<1> is tied to GTHE_CHANNEL.pcie3_7x_v1_4_i/inst/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1]
v2.0
v2.1
(Xilinx Answer 53151)Rate change back to Gen3 speed fails on x79 motherboardv1.3NA
(Xilinx Answer 50837)Some features in generated example design and testbench not verifiedv1.2Not Resolved Yet
(Xilinx Answer 47604)Incorrect Byte Count set when responding to Poisoned AtomicOp Requestv1.1NA


Other Information:

(Xilinx Answer 55085)Virtex-7 Gen3 Integrated Block Wrapper for PCI Express v2.0 - Verilog Instantiation Changed from Uppercase to Lowercase
(Xilinx Answer 57342)Virtex-7 FPGA Gen3 Integrated Block for PCI Express core SRIOV Example Design Simulation
(Xilinx Answer 58495)Xilinx PCI Express Interrupt Debugging Guide
(Xilinx Answer 64632)Virtex-7 FPGA Gen3 Integrated Block for PCI Express - How to enable 64 bit Prefetchable Memory Base/Limit Registers in TYPE1 Config Space?
(Xilinx Answer 57777)COMMON_CFG Attribute update for Production Silicon
(Xilinx Answer 58076)Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 - IES/GES devices support
(Xilinx Answer 57208)3DW TLP Header is Logged as 4DW TLP Header in the AER Header Log Register
(Xilinx Answer 58743)How can I share the same clocking module between two PCIe cores?

Revision History

04/03/2013Initial release
06/19/2013Updated for 2013.2
08/04/2013Added (Xilinx Answer 56975) and (Xilinx Answer 56976)
08/28/2013Added (Xilinx Answer 57208)
10/03/2013Added (Xilinx Answer 57777)
10/23/2013Updated for 2013.3
12/18/2013Updated for 2013.4
04/16/2014Updated for 2014.1
06/04/2014Updated for 2014.2
10/08/2014Updated for 2014.3
11/09/2014Added (Xilinx Answer 62296)
11/24/2014Updated for 2014.4 release
04/07/2015Added (Xilinx Answer 64153)
04/15/2015Updated for 2015.1 release
06/24/2015Updated for 2015.2 release
10/06/2015Updated for 2015.3 release
24/11/2015Updated for 2015.4 release
04/13/2016Updated for 2016.1 release
05/12/2016Added (Xilinx Answer 67172)
06/06/2016Added (Xilinx Answer 67111)
08/06/0216Updated for 2016.2 release
07/05/2016Added (Xilinx Answer 65569)
10/05/2016Updated for 2016.3 release

链接问答记录

子答复记录

AR# 54645
创建日期 02/28/2013
Last Updated 10/13/2016
状态 Active
Type 版本说明
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)