描述

This answer record contains the Release Notes and Known Issues for the LogiCORE IP Serial RapidIO Gen2 Core and includes the following:

• General Information
• Known and Resolved Issues
• Revision History
  

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward. 

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

解决方案

General Information

For LogiCORE IP Serial RapidIO Gen2 v1.7 release notes, see (Xilinx Answer 55339).

SRIO Gen2 v2.0 Rev1 Patch is available in (Xilinx Answer 55737).

SRIO Gen2 v2.0 Rev2 Patch is available in (Xilinx Answer 56660).

SRIO Gen2 v3.1 Rev2 Patch is available in (Xilinx Answer 56293).

Note: If Rev2 patch is installed, it is not necessary to install Rev1 patch first.

Supported Devices can be found in the following locations:

• Open the Vivado tool -> IP Catalog, right-click on an IP and select Compatible Families.

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Changes in v3.3

• Reduced transmit path latency by one clock in BUF layer(log_clk) and PHY layer(phy_clk) respectively
• Fixed functional issues around error injection and packet cancellation
• Updated GTH wrappers for current release
• Added fairness algorithm as user choice in GUI
• Transceiver control and status ports: added gt_txinhibit and gt_pcsrsvdin[]
  

Known and Resolved Issues

The following table provides known issues for the LogiCORE IP Serial RapidIO Gen2 core, starting with v2.0, initially released in Vivado Design Suite 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Other Information:

• (Xilinx Answer 55154) Design might not meeting timing for certain configurations of the core
• (Xilinx Answer 58402) Update to 7 series GTX Transceiver port RXDFEXYDEN

Revision History

链接问答记录

子答复记录