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AR# 54663

LogiCORE IP FIFO Generator - Release Notes and Known Issues for Vivado 2013.1 and newer tools

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE FIFO Generator and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE FIFO Generator IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/fifo_generator.html

解决方案

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v13.1 (Rev. 2)2016.3
v13.1 (Rev. 1)2016.2
v13.12016.1
v13.0 (Rev. 1)2015.4.2
v13.0 (Rev. 1)2015.4.1
v13.0 (Rev. 1)2015.4
v13.02015.3
v12.0 (Rev. 4)2015.2.1
v12.0 (Rev. 4)2015.2
v12.0 (Rev. 4)2015.1
v12.0 (Rev. 3)2014.4.1
v12.0 (Rev. 3)2014.4
v12.0 (Rev. 2)2014.3
v12.0 (Rev. 1)2014.2
v12.02014.1
v11.0 (Rev. 1)2013.4
v11.02013.3
v10.0 Rev 12013.2
v10.02013.1
v9.32012.4
v9.32012.3
v9.22012.2
v9.12012.1

General Guidance

The table below provides answer records for general guidance when using the LogiCORE IP FIFO Generator core.

Note: The "version found" column lists the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 42571)Virtex-5, Virtex-6, Spartan-6, 7 Series block RAM - Violating setup and hold on Enable can cause error in first Read or WriteNANA
(Xilinx Answer 67459)2016.1/2016.2 FIFO Generator: AXI Stream FIFO: m_axis_tvalid goes high after de-asserting the reset when there is no valid data written to the FIFOv13.1v13.1 Rev2
(Xilinx Answer 68034)FIFO Generator GUI resets subsequent tabs when number of synchronization stages option is changedv13.0 Rev1v13.1 Rev2
(Xilinx Answer 67706)WARNING: [IP_Flow 19-3374] seen when upgrading the 7-series project to UltraScale devicev13.1 Rev1NA
(Xilinx Answer 65299)2015.4: [IP_Flow 19-3664], [Synth 8-312] Warning messages seen in IP OOC Synthesis runv13.0 Rev1/ v8.3 Rev1
v13.1/ v8.3 Rev2
(Xilinx Answer 66627)2015.4: Verilog Behavioral models of FIFO generator, Block Memory Generator and Distributed Memory Generator IP'sv13.0 Rev1/ v8.3 Rev1v13.1/ v8.3 Rev2
(Xilinx Answer 62176)FIFO Generator v12.0 - Too many simulation warnings are generated from FIFO generator behavioral models during simulation. How safe is it to ignore these warnings?
v12.0v12.0 Rev4
(Xilinx Answer 56009)
FIFO Generator v9.3 - How to run Structural Simulation for built-in FIFO in the Vivado tool with standalone and multiple instances of the FIFO Generator core in the design
v12.0NA

Known and Resolved Issues

The following table provides known issues for the LogiCORE FIFO Generator core, starting with v10.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

  • No Known issue with this core

Change Log History

2016.3:

* Version 13.1 (Rev. 2)

* Port Change: wr_rst_busy and rd_rst_busy ports made available if safety circuit is enabled

* Bug Fix: HASH(0x10f31430)

* Feature Enhancement: Safety circuit is made independent of Output Register and Enable Reset Synchronization options

* Other: Added support for future devices

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

2016.2:

* Version 13.1 (Rev. 1)

* Revision change in one or more subcores

2016.1:

* Version 13.1

* Delivering only Verilog behavioral model.

* Constraint(s) for Independent Clocks Distributed RAM FIFO is changed, which may issue a CDC-1 warning that can be safely ignored.

* Output Register option is updated to offer either Embedded Register or Fabric Register or Both Embedded and Fabric Registers.

* Updated the FIFO Generator GUI to provide Embedded Register option for Built-in FIFO when ECC mode in selected.

* Programmable Full and Programmable Empty Threshold range has been reduced for UltraScale and UltraScale+ Built-in FIFO configurations. For more information on the exact threshold range change, refer to (PG057)

* Programmable Full and Programmable Empty Threshold values were reset to its default values when the previous version of the core is upgraded to the latest version. This has been corrected

* Revision change in one or more subcores

2015.4.2:

* Version 13.0 (Rev. 1)

* No changes

2015.4.1:

* Version 13.0 (Rev. 1)

* No changes

2015.4:

* Version 13.0 (Rev. 1)

* Fixed safety circuit related warnings in Behavioral model

2015.3:

* Version 13.0

* Additional safety circuit option provided for asynchronous reset configurations.

* Delivering only VHDL behavioral model.

* Added asymmetric port width support for 7-series Common Clock Block RAM FIFO

* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

2015.2.1:

* Version 12.0 (Rev. 4)

* No changes

2015.2:

* Version 12.0 (Rev. 4)

* No changes

2015.1:

* Version 12.0 (Rev. 4)

* Delivering non encrypted behavioral models.

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports

* Enabling behavioral simulation for Built-in FIFO configurations changes the simulation file names and delivery structure.

* Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:

* Version 12.0 (Rev. 3)

* No changes

2014.4:

* Version 12.0 (Rev. 3)

* Reduced DRC warnings.

* Internal device family change, no functional changes

* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time

2014.3:

* Version 12.0 (Rev. 2)

* Added support for Asynchronous AXI Stream Packet FIFO for UltraScale devices.

* Added support for write data count and read data count for Asynchronous AXI Stream Packet FIFO for UltraScale devices.

* Added support for write data count and read data count for Common Clock Block RAM FIFO when Asymmetric Port Width option is enabled for UltraScale devices.

* Added support for Low Latency Built-in FIFO for UltraScale devices.

2014.2:

* Version 12.0 (Rev. 1)

* Repackaged to improve internal automation, no functional changes.

2014.1:

* Version 12.0

* Asynchronous reset port (rst) for Built-in FIFO configurations is removed for UltraScale Built-in FIFO configurations. When upgrading from previously released core, 'rst' port will be replaced by 'srst' port.

* Synchronous reset (srst) mechanism is changed now for UltraScale devices. FIFO Generator will now provide wr_rst_busy and rd_rst_busy output ports. When wr_rst_busy is active low, the core is ready for write operation and when rd_rst_busy is active low, the core is ready for read operation.

* Added asymmetric port width support for Common Clock Block RAM FIFO, Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations for UltraScale Devices

* Added 'sleep' input port for Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations only for UltraScale Devices

* Internal device family name change, no functional changes

2013.4:

* Version 11.0 (Rev. 1)

* Added support for UltraScale devices

* Common Clock Built-in FIFO is set as default implementation type only for UltraScale devices

* Embedded Register option is always ON for Block RAM and Built-in FIFOs only for UltraScale devices

* Reset is sampled with respect to wr_clk/clk and then synchronized before the use in FIFO Generator only for UltraScale devices

2013.3:

* Version 11.0

* AXI ID Tags (s_axi_wid and m_axi_wid) are now determined by AXI protocol type (AXI4, AXI3). When upgrading from previously released core, these signals will be removed when AXI_Type = AXI4_Full.

* AXI Lock signals (s_axi_awlock, m_axi_awlock, s_axi_arlock and m_axi_arlock) are now determined by AXI Protocol type (AXI4, AXI3). When upgrading from previously released core, these signals width will reduce from 2-bits to 1-bit when AXI_Type=AXI4_Full

* Removed restriction on packet size in AXI4 Stream FIFO mode. Now, the packet size can be up to FIFO depth

* Enhanced support for IP Integrator

* Reduced warnings in synthesis and simulation

* Added support for Cadence IES and Synopsys VCS simulators

* Improved GUI speed and responsiveness, no functional changes

* Increased the maximum number of synchronization stages from 4 to 8. The minimum FIFO depth is limited to 32 when number of synchronization stages is > 4

2013.2:

* Version 10.0 (Rev. 1)

* Constraints processing order changed

2013.1:

* Version 10.0

* Native Vivado Release

* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.

Revision History

04/03/2013 - Initial release

 

AR# 54663
创建日期 02/28/2013
Last Updated 10/14/2016
状态 Active
Type 版本说明
器件
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite
IP
  • FIFO Generator