AR# 54667

LogiCORE IP 1G/2.5G Ethernet PCS/PMA or SGMII - Release Notes and Known Issues for Vivado 2013.1 and newer tools

描述

This answer record contains the Release Notes and Known Issues for the 1G/2.5G Ethernet PCS/PMA or SGMII Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tools.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE IP Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/do-di-gmiito1gbsxpcs.html

Note: Prior to the 2015.1 release, the core was named Ethernet1000BASE-X PCS/PMA or SGMII as 2.5G support was not added.

解决方案

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v16.2 (Rev. 1)2020.2
v16.22020.1
v16.1 (Rev. 7)2019.2
v16.1 (Rev. 6)2019.1
v16.1 (Rev. 5)2018.3
v16.1 (Rev. 4)2018.2
v16.1 (Rev. 3)2018.1
v16.1 (Rev. 2)2017.4
v16.1 (Rev. 1)2017.3
v16.12017.2
v16.0 (Rev. 2)2017.1
v16.0 (Rev. 1)2016.4
v16.02016.3
v15.2 (Rev. 1)2016.2
v15.22016.1
v15.1 (Rev. 1)2015.4
v15.12015.3
v15.0 (Rev. 1)2015.2
v15.02015.1
v14.3 (Rev. 1)2014.4
v14.32014.3
v14.2 (Rev. 1)2014.2
v14.22014.1
v14.12013.4
v14.02013.3
v13.02013.2
v12.02013.1
v11.52012.4
v11.42012.2
v11.32012.1


General Guidance

The table below provides answer records for general guidance when using the LogiCORE IP1G/2.5G Ethernet PCS/PMA or SGMII core.

Answer RecordTitle
(Xilinx Answer 38279)Ethernet IP Solution Center
(Xilinx Answer 55077)Ethernet IP Cores - Design Hierarchy in Vivado

 

Design Advisory

The table below provides design advisory for general guidance when using the LogiCORE IP 1G/2.5G Ethernet PCS/PMA or SGMII core.
Answer RecordTitle
(Xilinx Answer 64835)Design Advisory for 1G/2.5G Ethernet PCS/PMA or SGMII v15.0 (Rev1) and earlier - Fabric Elastic Buffer overflow will cause RXBUFERR to toggle and Auto-Negotiation to restart and never complete

Known and Resolved Issues

The following table provides known issues for the 1G/2.5G Ethernet PCS/PMA or SGMII core, starting with v12.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion
Found
Version
Resolved
N/AFixed the BOTH configuration option visibility based on the GT availability2020.12020.2
N/AFixed a GUI issue where while selecting the 1000BaseX over LVDS, the LVDS refclk option should not be visible2020.12020.2
N/AUpdated the fix for auto-neg restart self clear for cl372018.32019.1
N/AUpdated the rxuserclk/rxuserclk2 clock generation with BUFGCE and where CE is connected to MMCM_LOCKED2018.12018.2
N/AUpdated the REFCLK pin frequency for IDELAYE2 based on the input clock2017.42018.1
N/AFixed the lvds refclk selection based on synchronous and asynchronous clock configuration in the GUI2017.42018.1
N/AGTY port GTRXRESET disturbing TX data2017.22017.3
(Xilinx Answer 69494)VCU118 / KCU116 - How to bring up the SGMII PHY2017.2See Answer Record
(Xilinx Answer 67883)1G/2.5G Ethernet PCS/PMA or SGMII for UltraScale/UltraScale+ v15.2 (Rev1) and earlier - Fabric Elastic Buffer overflow will cause RXBUFERR to toggle and Auto-Negotiation to restart and never completev15.2(Rev.1)2016.3
(Xilinx Answer 66031)1G/2.5G Ethernet PCS/PMA or SGMII v15.1 (Rev.1) - Auto-Negotiation intermittently fails to complete with the corev151 (Rev1)2016.1
(Xilinx Answer 66030)1G/2.5G Ethernet PCS/PMA or SGMII v15.1 - Auto-Negotiation intermittently fails to complete with the corev15.12016.1
 1G/2.5G Ethernet PCS/PMA or SGMII v15.0 (Rev1) or earlier - LVDS Transceiver - Soft reset can cause data corruption in LVDS Transceiverv15.0 (Rev1)2015.3
(Xilinx Answer 64224)1G/2.5G Ethernet PCS/PMA or SGMII v15.0 - Timing failure on RST pin on IDELAYCTRv15.02015.3
(Xilinx Answer 64143)1G/2.G Ethernet PCS/PMA or SGMII v15.0 - Simulation errors are seen for UltraScale GTHE3 modelv15.0See Answer Record
(Xilinx Answer 63844)LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v14.3 or earlier - UltraScale SGMII over LVDS - The core does not recover from sporadic application of resetsv14.3 (Rev1)v15.0
(Xilinx Answer 62072)Ethernet 1000BASE-X PCS/PMA or SGMII - UltraScale - SGMII over LVDS Synchronization intermittently lostv14.3 (Rev1)v15.0
(Xilinx Answer 63441)UltraScale GTH - free running clock updatev14.3v15.0
(Xilinx Answer 62900)UltraScale - 1000BASE-X over LVDS not supportedv14.3See Answer-Record
(Xilinx Answer 62666)7 Series - GTX/GTH - Intermittent link up failures seenv14.3v14.3 (Rev. 1)
(Xilinx Answer 62072)UltraScale - SGMII over LVDS Synchronization intermittently lostv14.2NA
(Xilinx Answer 62377)SGMII - 7 Series Transceiver interface with Fabric Elastic Buffer - Auto-Negotiation can fail to completev14.2v14.3
(Xilinx Answer 62359)7 Series - Link does not come back up after Cable pull/replug or link partner resetv14.1v14.3 (Rev. 1)
(Xilinx Answer 60784)GTP and GTH - Production reset DRP sequence could get in hung state that requires reconfiguration to recoverv14.2v14.2 (Rev. 1)
(Xilinx Answer 60204)SGMII and 1588 - Updated XDC constraints needed to meet timingv14.2Work-around in answer record
(Xilinx Answer 60086)Verilog - SGMII over LVDS - Synthesis Failsv14.2v14.2 (Rev. 1)
(Xilinx Answer 58020)MMCM_LOCKED output needs to be connected to reset logicv14.0v14.1
(Xilinx Answer 55360)mmcm_locked not connected to GT tx_startup_fsm and rx_startup_fsmv12.0 specificWork-around in answer record
(Xilinx Answer 55367)7 Series GTP and GTH - Update to RX terminationv12.0v14.0
(Xilinx Answer 53779)Virtex-7 GTH Transceiver - RX Reset Sequence Requirement for Production Siliconv11.4v12.0
(Xilinx Answer 53561)Artix-7 - RX Reset Sequence Requirement for Production Siliconv11.4v12.0
N/ASynchronization logic added to 7 Series GT tx_startup_fsm and rx_startup_fsm inputsv11.4v12.0
(Xilinx Answer 53444)After disabling AN, AN sequences may still be transmitted if core has not gained Synchronization yetv11.4

v12.0

链接问答记录

子答复记录

AR# 54667
日期 11/27/2020
状态 Active
Type 版本说明
Tools
IP