的页面

AR# 54673

MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled

Description

Version Found: MIG 7 Series 1.8
Version Resolved: See (Xilinx Answer 45195)

When generating a MIG 7 Series DDR3 design with Debug Signals enabled, a few of the Write Leveling Calibration debug signals are not connected properly to the Write ILA ChipScope core.

The incorrect connections are on

wl_po_coarse_cnt,
wl_po_fine_cnt,
rd_data_edge_detect_r,
and
wl_edge_detect_valid_r.

This answer record shows how to manually correct these ILA connections until this issue is resolved in a future MIG 7 Series release.

解决方案

The user_design/rtl/core_name.v module includes the connection of the debug signals to the ChipScope ILA cores.

Open this module and locate the "ILA for monitoring write path signals" section.

The required connection updates are shown below.

The port numbers in comments are the old/incorrect connections.

//*******************************************************
   //     - ILA for monitoring write path signals,
   //       and synchronized read data
   //*******************************************************

   assign rd_data_edge_detect_r = dbg_phy_wrlvl[67+:9]; //66
   assign wl_po_fine_cnt         = dbg_phy_wrlvl[76+:54]; //75
   assign wl_po_coarse_cnt       = dbg_phy_wrlvl[130+:27]; //129

assign ddr3_ila_wrpath[10] = dbg_phy_wrlvl[60]; //59 // wl_edge_detect_valid_r

assign ddr3_ila_wrpath[96+:54] = dbg_phy_wrlvl[76+:54]; //75
assign ddr3_ila_wrpath[150+:27]= dbg_phy_wrlvl[130+:27]; //129

本答复记录是否对您有帮助？

链接问答记录

主要问答记录

Answer Number	问答标题	问题版本	已解决问题的版本
67815	[Synth 8-4169] error in use clause: package 'vcomponents' not found in library 'xpm'	N/A	N/A
67818	Zynq UltraScale+ MPSoC: 2016.3 PMUFW Loading via JTAG / SD Boot Modes and Running An Example	N/A	N/A
67819	Zynq UltraScale+ MPSoC: 2016.3 PMUFW, How to add custom initialization code.	N/A	N/A
		N/A	N/A
67449	High Speed SelectIO Wizard - How to create multiple instances of the same setup	N/A	N/A
67442	JESD204B - A simplified approach to achieving robust repeatable latency	N/A	N/A
67440	AXI Bridge for PCI Express Gen3 (Vivado 2016.1) - [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'axi_pcie3_0'. Failed to generate 'Examples' outputs:	N/A	N/A
		N/A	N/A
674	SPROMS, Markings - The XC1700 Ordering ID (part number) and PROM Marking ID are different for the same part	N/A	N/A
67544	DDR4/DDR3 UltraScale IP - Data errors seen at user interface when using Normal Ordering Error. The errored data presented is correct data from a later read from the same address. App_rdy might get stuck low.	N/A	N/A
67543	Vivado 系统生成器 v2016.2 — 无法通过运行系统生成脚本，在 Ubuntu 14.04 中配置和启动 Matlab。	N/A	N/A
67548	ECO : Next Generation FPGA Editor	N/A	N/A
		N/A	N/A
67684	UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problems	N/A	N/A
6768	Virtex/-E/-II/-II Pro/-4/-5 - Are Virtex devices hot-swap compliant?	N/A	N/A
67780	SDK becomes non-responsive when I try to change the BSP setting on an Ubuntu 14 Virtual Machine	N/A	N/A
67787	2015.4 Vivado — 实现方案设置改变时，比特流 tcl.post 设置被删除	N/A	N/A
		N/A	N/A
		N/A	N/A
67414	Zynq UltraScale+ MPSoC: 2016.2/2016.1 FSBL unable to load PMU_FW in SD and eMMC boot mode on ZCU102 board	N/A	N/A
67412	Zynq UltraScale+ MPSoC: 2016.2 FSBL, Added DDR ECC Initialization feature	N/A	N/A
67416	2016.1 PetaLinux - Installer Automatically Appends Sub-Directory to Target Installation Path	N/A	N/A
		N/A	N/A
67925	LogiCORE Video PHY Controller, Software Driver v1.1 - Why do I see intermittent training problems, or have trouble with training more than one lane?	N/A	N/A
67922	RLDRAM3 IP - Example Design - Advanced Traffic Generator (ATG) detects data compare errors when testing with the TG_MAX_NUM_OF_ITER_ADDR parameter is set to a large value	N/A	N/A
67923	2016.2 PetaLinux Zynq UltraScale+ MPSoC GMII2RGMII on MACB driver	N/A	N/A
67927	HDMI Transmitter Subsystem v2.0 (Rev. 1) - Why do I sometimes see failures when performing HDCP Authentication?	N/A	N/A
67924	LogiCORE Video PHY Controller, Software Driver v1.1 - Video PHY Controller Software Driver v1.1 Patch Download	N/A	N/A
		N/A	N/A
67041	软错误缓解 (SEM) IP — 在 Vivado IP 集成器 (IPI) 中使用 UltraScale SEM IP	N/A	N/A
67045	HDMI RX Subsystem - Do the DDC Signals need to be connected if using the HDMI core in DVI only mode without HDCP?	N/A	N/A
67043	JESD204 v6.1, v6.2, v7.0 and JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - Defaults to DFE Equalisation mode	N/A	N/A
67044	JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - TXDIFFCTRL low default value	N/A	N/A
6704	3.1i Design Manager - How do I specify files (EDN, EDF, VHD, VER, SCH, etc.) to be automatically copied to my version or revision subdirectories for maintenance?	N/A	N/A
67141	Simulation Libraries - Can I use UNIMACRO libraries in UltraScale and UltraScale Plus?	N/A	N/A
67144	UltraScale+ PCI Express Integrated Block (Vivado 2016.1) - Incorrect GT Quad Location for Virtex 9P Devices	N/A	N/A
67145	Zynq UltraScale+ MPSoC, Vivado 2016.1 - ILA/IBA cores are not found in Vivado Hardware Manager for ZU3 and ZU15 devices	N/A	N/A
67142	2016.1 - Simulation - Project Utilities Tcl App update required for Export Simulation	N/A	N/A
		N/A	N/A
67280	2016.1 Zynq UltraScale+ MPSoC: FSBL fails to load the PMUFW	N/A	N/A
6728	1.5i SP2 Virtex Map - Crash during map.	N/A	N/A
67384	Vivado - [Place 30-678] Failed to do clock region partitioning	N/A	N/A
67382	Vivado Simulation - compile_simlib targetting ModelSim DE fails on Linux 64-bit OS	N/A	N/A
67381	2016.1 Vivado Hardware Manager: Incorrect IDCODES shown in Vivado Hardware Manager GUI for some UltraScale devices	N/A	N/A
6738	HP 1.5i Install : 1 archive had fatal errors. file #0. bad zipfile offset (lseek): 0	N/A	N/A
67897	Modular Media over IP RFC4175 De-Packetizer - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions	N/A	N/A
67895	2016.4 Vivado IP Flows - When packaging a block design (BD) containing a MicroBlaze block, I get the warning: CRITICAL WARNING: [IP_Flow 19-4791] Block design with Microblaze subdesign IP 'my_design_microblaze_0_0' should be packaged with the XCI option	N/A	N/A
67892	QuestaSim - Fatal: (vsim-12005) Undefined function '_ZN5boost6system15system_categoryEv' introduced from '/Xilinx/VIVADO/Vivado/2016.1/lib/lnx64.o/librdi_commonxillic.so' is being called	N/A	N/A
67893	2016.2 Download - Downloading Vivado on Windows 10, the browser states "The signature of Xilinx_Vivado_SDK_2016.2_0605_1_Win64.exe is corrupt or invalid"	N/A	N/A
67898	Modular Media over IP RFC3190 De-Packetizer - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions	N/A	N/A
67890	2016.3 - Vivado Simulator - Scope for pre-compiled IP instance is missing in Scope Window	N/A	N/A
67899	Modular Media over IP RFC4175 Packetizer - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions	N/A	N/A
67891	DDR4/DDR3 IP - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode	N/A	N/A
67896	MIPI CSI-2 Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions	N/A	N/A
6789	1.5i SpartanXL PAR - Divide by Zero crash	N/A	N/A
67522	SDSoC - SDDebug and SDRelease build configurations decoupled	N/A	N/A
67523	SDSoC - Passing command line arguments to executable with Performance Estimation	N/A	N/A
67520	MIG 7 Series DDR3 - Periodic reads used for VT tracking might be missing during continuous write transactions	N/A	N/A
67528	How to speed up "10G/25G Ethernet Subsystem" simulation	N/A	N/A
67521	SDSoC - SDSoC 2016.2 - Release Notes and Known Issues	N/A	N/A
6752	Obselete 1.5i JTAG Programmer - SP2 Patch update-9500XL/Win95 error when programming (Error:basut - Check the target power supply is stable...)	N/A	N/A
67820	Zynq UltraScale+ MPSoC: 2016.3 PMUFW, Error Management	N/A	N/A
67828	Zynq UltraScale+ MPSoC: Linux SPI interrupts mapping	N/A	N/A
67824	2016.2 Virtex UltraScale+ - Clock Placer can fail to partition UltraScale+ designs due to not properly accounting for PS8 blocks interference with clock routing	N/A	N/A
6782	NGDBUILD netlist priority: What's the searching order NGDBUILD uses to merge hierarchical modules into a .ngd file	N/A	N/A
67499	2016.2 Vivado - Loading a synthesized or implemented design in Vivado gives an Internal Exception and the error message "Xgd File 'xc****.xgd' is missing"	N/A	N/A
67491	High Speed SelectIO Wizard - Unable to select the SLVS IOSTANDARD	N/A	N/A
6749	Virtex Configuration - The DONE pin does not go High, and the INIT pin does not go Low	N/A	N/A
671	Error cl192 or cl126 while converting a PALASM (PDS) file	N/A	N/A
67558	Vivado - ERROR: [Project 1-589] Checkpoint part '(part name)-es2' is not available. Closest-matching available part(s): (part name)	N/A	N/A
67553	2016.2 - SDSoC - ZC706_mem platform failing	N/A	N/A
67551	Vivado Simulator does not give any warning or error message when an integer goes out of range	N/A	N/A
		N/A	N/A
67651	Zynq UltraScale+ MPSoC, PS DDR - Video Class Traffic Might Underrun When DDR ECC Is Enabled	N/A	N/A
		N/A	N/A
67796	ERROR: [VRFC 10-449] cannot open file "/afs/xxxx/obsfdacmj4ltsh34hqceamceyrcimraog5opt0hdnxd.sdb" for writing	N/A	N/A
67793	MIPI CSI-2 Receiver Subsystem v2.0 (Rev. 1) - Why do I see timing failing on the video_aresetn when using two CSI-2 Receiver Subsystems with one as a master and one as a slave?	N/A	N/A
		N/A	N/A
67013	2016.1 - compile_simlib fails with 3-4 errors for all simulators when the -ise_install_path option is used	N/A	N/A
67010	Vivado HLS 2016.1 : Why does the perfect loop example have poorer performance versus the imperfect loop example?	N/A	N/A
67015	2016.1 - compile_simlib - Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)	N/A	N/A
67012	2016.x Vivado Simulator - Known Issues	N/A	N/A
6701	VERILOG-XL - How do I run simulation with Verilog-XL?	N/A	N/A
67420	2016.2 XEN test is not working on Zynq UltraScale+ MPSoC boards in QEMU	N/A	N/A
67426	SDSoC - Cannot debug application when targeting a custom platform	N/A	N/A
67421	DMA Subsystem for PCI Express (Vivado 2016.2) - Prefetchable support for 64-bit BAR	N/A	N/A
67422	UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2016.2) - Link up failure after multiple resets	N/A	N/A
67427	Zynq UltraScale - How can I debug a Linux application running on a Zynq UltraScale QEMU	N/A	N/A
		N/A	N/A
679	Obselete : Could not get model for statbar!	N/A	N/A
67938	2016.X - Simulation - ModelSim generates error when simulating XPM	N/A	N/A
67936	Vivado - ERROR: [Project 1-202] Error writing the XML file 'Z:/eda/myproj/myproj.xpr'	N/A	N/A
67933	UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.	N/A	N/A
67931	1G/2.5G Ethernet PCS/PMA or SGMII v15.2 - SGMII over LVDS option is not enabled in GUI for devices which do not have Transceivers	N/A	N/A
67939	Soft Error Mitigation (SEM) IP – Location of the makedata.tcl file has changed in Vivado 2016.3	N/A	N/A
67930	2016.2 PetaLinux Zynq UltraScale+ MPSoC GEM Clock Control needs to set for EMIO clock for RX	N/A	N/A
		N/A	N/A
67098	2016.1 UltraScale Implementation - New DRC check for clock routing in UltraScale results in both new positive and false-positive errors.	N/A	N/A
67097	Vivado Device Programmer - 2016.1 VU440 BBR programming failure	N/A	N/A
6709	FPGA Configuration - Done pin does not go high, Startup block is used	N/A	N/A

AR# 54673
日期	08/18/2014
状态	Active
Type	已知问题
器件	Artix-7 Kintex-7 Virtex-7
IP	MIG 7 Series

AR# 54673

MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled

Description

解决方案

链接问答记录

主要问答记录

应用

产品

开发者专区

技术支持

关于 Xilinx