Version Found: MIG 7 Series 1.8
Version Resolved: See (Xilinx Answer 45195)
When generating a MIG 7 Series DDR3 design with Debug Signals enabled, a few of the Write Leveling Calibration debug signals are not connected properly to the Write ILA ChipScope core.
The incorrect connections are on
This answer record shows how to manually correct these ILA connections until this issue is resolved in a future MIG 7 Series release.