This answer record contains the Release Notes and Known Issues for LogiCORE IP AXI Bus Functional Models (AXI BFM) and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP AXI Bus Functional Models Core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/do-axi-bfm.html
General Information
Supported Devices can be found in the following three locations:
| Core Version | Vivado Tools Version |
|---|---|
| v5.0 (Rev. 7) | 2015.3 |
| v5.0 (Rev. 6) | 2015.2 |
| v5.0 (Rev. 5) | 2015.1 |
| v5.0 (Rev. 4) | 2014.3 |
| v5.0 (Rev. 3) | 2014.2 |
| v5.0 (Rev. 2) | 2014.1 |
| v5.0 (Rev. 1) | 2013.4 |
| v5.0 | 2013.3 |
| v4.1 | 2013.2 |
v4.0 | 2013.1 |
| v3.0 | 2012.4 |
General Guidance
For general guidance on how to use this core, please refer to LogiCORE IP AXI Bus Functional Models Data Sheet for more details.
For Licensing, please refer to (Xilinx Answer 61473).
Design Assistant
Here are some example designs and extra information for the core:
Article Number | Article Title |
|---|---|
| (Xilinx Answer 62769) | 2014.2 Vivado - AXI BFM IPI example design |
| (Xilinx Answer 57551) | Example Design - Simulating the AXI DMA core in IPI using the AXI BFMs |
| (Xilinx Answer 57069) | 14.x/2013.x (Linux) - AXI BFM - License Issues with 3rd party Simulators |
| (Xilinx Answer 55464) | AXI BFM - Licensing Information |
| (Xilinx Answer 56383) | 2013.1 Vivado IPI - Example of using AXI BFM models in IPI |
| (Xilinx Answer 52581) | 2012.x - AXI BFM - Tool Support for AXI Bus Functional Model |
Article Number | Article Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 67207) | Vivado 2016.1 AXI BFM, Zynq BFM - AXI BFM and Zynq BFM do not correctly terminate WSTRBs of unaligned burst writes | 2016.1 | See Answer Record |
| (Xilinx Answer 63392) | ModelSim DE/PE - How do I run the AXI BFM Example Design in Vivado 2014.4? | 2014.4 | See Answer Record |
| (Xilinx Answer 60841) | 2014.1 AXI BFM - ERROR: RVALID from slave is not zero (reset value) - AMBA AXI SPEC V2 - Section 11.1.2 Reset | 2014.1 | 2014.3 |
| (Xilinx Answer 59667) | Vivado/ModelSim - ModelSim fails on PLI (AXI BFM) with "Error: (vsim-3193)" and "Error: (vsim-PLI-3002)" | 2013.2 | See Answer Record |
| (Xilinx Answer 56684) | 2013.x - How do you run AXI BFM simulation with NCSim? | v4.1 | v5.0 |
| (Xilinx Answer 58164) | 2013.x - How do you run AXI BFM simulation with VCS? | v4.0 | N/A |
| (Xilinx Answer 52759) | 2012.2 Vivado IP Flows - Synthesizing the AXI BFM core results in "ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified" | 3.0 | N/A |
| (Xilinx Answer 54680) | AXI Bus Functional Model v3.0 - Cannot generate this version in 14.4 Coregen/XPS | v3.0 | N/A |
Revision History:
04/03/2013 - Initial Release
| AR# 54678 | |
|---|---|
| 日期 | 06/10/2016 |
| 状态 | Active |
| Type | 版本说明 |
| 器件 |
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| IP |
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