This answer record contains the Release Notes and Known Issues for the AXI Ethernet Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and later tool versions.
AXI Ethernet LogiCORE IP Page:
Note: Prior to the 2015.1 release, the AXI 1G/2.5G Ethernet Subsystem Core was called AXI Ethernet as we did not have 2.5G support.
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|V6.0 (Rev .1)||2013.4|
|v6.1 (Rev. 1)||2014.2|
|v6.2 (Rev. 1)||2014.4|
|v7.0 (Rev. 1)||2015.2|
|v7.0 (Rev. 2)||2015.3|
|v7.0 (Rev. 3)||2015.4|
|v7.0 (Rev. 4)||2016.1|
|v7.0 (Rev. 5)||2016.2|
|v7.0 (Rev. 6)||2016.3|
|v7.0 (Rev. 7)||2016.4|
|v7.0 (Rev. 8)||2017.1|
|v7.1 (Rev. 1)||2017.3|
|v7.1 (Rev. 2)||2017.4|
|v7.1 (Rev. 3)||2018.1|
|v7.1 (Rev. 4)||2018.2|
|v7.1 (Rev. 5)||2018.3|
|v7.1 (Rev. 6)||2019.1|
|v7.1 (Rev. 7)||2019.2|
The table below provides answer records for general guidance when using the LogiCORE AXI Ethernet core.
|(Xilinx Answer 55248)||Vivado Timing and IP Constraints|
Known and Resolved Issues
The following table provides known issues for the AXI 1G/2.5G Ethernet Subsystem core, starting with v4.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version |
|(Xilinx Answer 73409)||2019.2 - 1G/2.5G AXI Ethernet Subsystem - TLAST will be asserted for two consecutive beats when a slave deasserts TREADY before the last beat on an AXIS interface||v7.1 (Rev. 7)||See Answer Record|
|(Xilinx Answer 69455)||1G/2.5G AXI Ethernet Subsystem v7.1 and earlier - Lwip stopped working with attaching IPs on axi4stream interface||v7.0 (Rev. 8)||See Answer Record|
|(Xilinx Answer 65767)||2015.3 AXI Ethernet designs with LwIP software are not working correctly in KCU105, VCU108 and VCU110 UltraScale boards||7.0 (Rev. 2)||See Answer Record|
|(Xilinx Answer 64241)||AXI 1G/2.5G Ethernet Subsystem v7.0 - The core currently does not meet timing on 2.5G designs for -2L and -1LV devices||v7.0||See Answer Record|
|(Xilinx Answer 64833)||2015.1 AXI Ethernet/RGMII - LWIP is not working on Artix devices.||v7.0||v7.0 (Rev1)|
|(Xilinx Answer 64223)||Vivado IPI - AXI 1G/2.5G Ethernet Subsystem v6.2 or earlier - UltraScale SGMII over LVDS - idelay control element needs to be added manually for IPI design||v6.2||See Answer Record|
|(Xilinx Answer 64142)||Vivado IPI - AXI 1G/2.5G Ethernet Subsystem v6.2 or earlier - UltraScale SGMII over LVDS - Synchronization and reset issue||v6.2||See Answer Record|
|(Xilinx Answer 63106)||LogiCORE Tri-Mode Ethernet MAC, 10-Gigabit Ethernet MAC, AXI Ethernet and AXI 10G Ethernet- Vivado 2014.4 and earlier - AXI lite interface failures seen when using 64-bit master||v6.2||See Answer Record|
|(Xilinx Answer 63914)||AXI Ethernet v6.2 or earlier - UltraScale - SGMII over LVDS - Synchronization and reset issue||v6.2||See Answer Record|
|(Xilinx Answer 56024)||AXI Ethernet v4.0 - SGMII interface is incorrectly configured for Auto-negotiation||v4.0||v5.0|
|(Xilinx Answer 58343)||AXI Ethernet v6.0 system configured in FIFO mode fails peripheral tests owing to a Vivado tool issue||v6.0||v6.0|
|(Xilinx Answer 59504)||Occasionally PHY_RESET_N is not de-asserted after powerup||v2.01.a||v6.1|