UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54690

40G/50G Ethernet SubSystem - IP Release Notes and Known Issues for LogiCORE 40G/50G Ethernet Core for Vivado 2016.1 and Forward

描述

This answer record contains the Release Notes and Known Issues for the 40G/50G Ethernet Subsystem and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2016.1 and forward.

40G/100G Ethernet Core LogiCORE IP Page:

https://www.xilinx.com/products/intellectual-property/ef-di-50gemac.html

解决方案

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core
Version
Vivado Tool
Version
v2.22017.2
v2.12017.1
v2.0 (Rev. 1)2016.4
v2.02016.3
v1.12016.2
v1.02016.1

General Guidance
The table below provides Answer Records for general guidance when using the LogiCORE 40G/100G Ethernet core.

Article NumberArticle Title
(Xilinx Answer 67675)Simulation Speed Up


Known and Resolved Issues

The following table provides known issues for the 40G/50G High Speed Ethernet Subsystem, initially released in the Vivado 2016.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion
Found
Version
Resolved
(Xilinx Answer 69612)Update needed for intermittent link up if using Auto-Negotiation and Link Trainingv2.0See AR
(Xilinx Answer 69568)Incorrect Alignment Marker Spacing used if generating core with RS-FEC, but not enabling RS-FECv2.0v2.2
(Xilinx Answer 68731)40G core, no support for -1 speed grade v2.0v2.1
(Xilinx Answer 67612)Patch Updates for block lock issue in 40G core v1.2v2.0
(Xilinx Answer 67256)How can the core be targeted to Kintex UltraScale/ Kintex UltraScale+ devices v1.1v1.2
AR# 54690
日期 08/11/2017
状态 Active
Type 版本说明
IP
  • 40G/100G Ethernet Core
的页面