UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54778

Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - keep, keep_hierarchy, ram_style, rom_style

Description

This Answer record describes the Vivado Synthesis Attributes keep, keep_hierarchy, ram_style, rom_style, and also provides coding examples for them. The coding examples are attached to this answer record. The AR also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the Synthesis attributes covered in each example.

解决方案

KEEP

The KEEP attribute is used to prevent optimizations in which signals are optimized or absorbed into logic blocks. The attribute instructs the synthesis tool to keep the signal it was placed on, and that signal is placed in the netlist.

KEEP is commonly used in conjunction with timing constraints. If there is a timing constraint on a signal that would normally be optimized, KEEP will prevent this and allow the correct timing rules to be used.

In cases where other attributes are in conflict with KEEP, the KEEP attribute usually takes precedence over them:

  • When you have a MAX_FANOUT attribute on a signal and a KEEP on a second signal driven by the first, the KEEP on the second signal will not allow fanout replication.
  • With RAM_STYLE="block", when there is a KEEP on the register that would need to become part of the RAM, the KEEP attribute prevents the block RAM from being inferred.

Accepted values are:

  • true : Keeps the signal.
  • false : Allows Vivado Synthesis to optimize if necessary. False does not force the tool to remove the signal. The default value is false.

Notes:

  • The KEEP attribute does not force the place and route tool to keep the signal. Instead, this is accomplished using the DONT_TOUCH attribute.
  • The KEEP attribute is not supported on the port of a module or entity. If specific ports are needed to be kept, either use the flatten_hierarchy = none setting, or put a DONT_TOUCH on the module or entity itself.
  • Take care with the KEEP attribute on signals that are not used in the RTL later. Synthesis keeps those signals, but they do not drive anything. This could cause issues later in the flow.
  • It is recommended to set this attribute in the RTL only. Because signals that need to be kept are often optimized before the XDC file is read, setting this attribute in the RTL ensures that the attribute is used.

Verilog Example

(* keep = "true" *) wire  sig1;

VHDL Example

signal sig1 : std_logic;

attribute keep : string;

attribute keep of sig1 : signal is "true";

Known Issues:

N/A


KEEP_HIERARCHY

The KEEP_HIERARCHY attribute is used to prevent optimizations along the hierarchy boundaries. The Vivado synthesis tool attempts to keep the same general hierarchies specified in the RTL, but it can flatten or modify them for QoR reasons.

If KEEP_HIERARCHY is placed on the instance, the synthesis tool keeps the boundary on that level static. This can affect QoR and also should not be used on modules that describe the control logic of 3-state outputs and I/O buffers.

The KEEP_HIERARCHY attribute can be placed in the module, architecture level, or the instance.

Accepted values are:

  • yes : Preserves the hierarchy on the level specified.
  • no : Hierarchical blocks are merged into the top level module.

Verilog Example

On Module:

(* keep_hierarchy = "yes" *) module bottom (in1, in2, in3, in4, out1, out2);

On Instance:

(* keep_hierarchy = "yes" *) bottom u0 (.in1(in1), .in2(in2), .out1(temp1));

VHDL Example

On Module:

attribute keep_hierarchy : string;

attribute keep_hierarchy of beh : architecture is "yes";

On Instance:

attribute keep_hierarchy : string;

attribute keep_hierarchy of u0 : label is "yes";

Known Issues:

N/A


RAM_STYLE

RAM style controls how the Vivado Synthesis tool infers memory. Accepted values are:

  • block : Instructs the tool to infer RAMB type components.
  • distributed : Instructs the tool to infer LUT RAMs.

By default, the tool will select which RAM to infer based on heuristics that give the best results for the most designs. Place this attribute on the array that is declared for the RAM.

Verilog Example

(* ram_style = "distributed" *) reg [data_size-1:0] myram [2**addr_size-1:0];

VHDL Example

attribute ram_style : string;

attribute ram_style of myram : signal is "distributed";

Known Issues:

N/A


ROM_STYLE

ROM style controls how the Vivado Synthesis tool infers ROM memory. Accepted values are:

  • block : Instructs the tool to infer RAMB type components.
  • distributed : Instructs the tool to infer LUT ROMs.

By default, the tool will select which ROM to infer based on heuristics that give the best results for the most designs.

Verilog Example

(* rom_style = "distributed" *) reg [data_size-1:0] myrom [2**addr_size-1:0];

VHDL Example

attribute rom_style : string;
attribute rom_style of myrom : signal is "distributed";
 
Known Issues:
N/A
 
Table 1:
 
File Name Attribute Example
keep.zip KEEP
keep_hierarchy.zip KEEP_HIERARCHY
ram_style.zip RAM_STYLE
rom_style.zip ROM_STYLE
 

Attachments

文件名 文件大小 File Type
keep.zip 1 KB ZIP
keep_hierarchy.zip 1 KB ZIP
ram_style.zip 1 KB ZIP
rom_style.zip 1 KB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
55160 Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support N/A N/A
AR# 54778
创建日期 03/06/2013
Last Updated 06/04/2014
状态 Active
Type 解决方案中心
Tools
  • Vivado Design Suite