描述

This answer record contains the Release Notes and Known Issues for the AXI4-Stream Interconnect (axis_interconnect) Core and includes the following:

• General Information
• Known and Resolved Issues
• Revision History
  

The following sub-modules are included:

• axis_interconnect
• axis_broadcaster
• axis_clock_converter
• axis_combiner
• axis_data_fifo
• axis_dwidth_converter
• axis_register_slice
• axis_subset_converter
• axis_switch

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

Please reference the IP Release Notes Guide (XTP025) for past known issue logs and ISE design tools support information:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

LogiCORE IP AXI4-Stream Interconnect Core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/axi4-stream_interconnect.html

解决方案

General Information

Supported Devices can be found in the following three locations:

• LogiCORE IPAXI4-Stream Interconnect Core Product Guide
• LogiCORE IP AXI4-Stream Interconnect Core IP Page
• Open the Vivado software -> IP Catalog, right click on an IP and select "Compatible Families"

For a list of new features and added device support for all versions, see the Change Log file available with the core in the Vivado tool.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1:  Version

Table 2: General Guidance

Table 2 provides answer records for general guidance when using the LogiCORE IP AXI4-Stream Interconnect core.

Known and Resolved Issues

The following table provides known issues for the AXI4-Stream Interconnect core, starting with v1.1, initially released in Vivado 2012.4 tools.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
4/03/2013 - Initial release