Version Found: v1.8
Version Resolved: See (Xilinx Answer 45195)
No VHDL instantiation template (.vho file) is provided with MIG. In the CORE Generator tool, when the design entry is set to VHDL, only a verilog instantiation template (.veo) is generated.
This is a known issue.
To work around this problem, use the instantiation in the example_top.vhd as a reference. The component declaration and instantiation for the user design can be copied directly from within example_top.vhd.
Revision History
04/03/2013 - Initial release
| AR# 54845 | |
|---|---|
| 日期 | 12/02/2013 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 |
|
| IP |
|