描述

I am running into throughput and throttling issues from the AXI VDMA itself (i.e., the interconnect is sitting idle waiting for transactions, but I am getting throttled on the stream side of the AXI VDMA).

What is wrong?

解决方案

There is a known limitation with the core (it is actually a limitation of the AXI Datamover upon which the AXI VDMA is built) where throughput suffers greatly if your stream-side clocks are faster than your memory map-side clocks.

Please ensure that your memory map clocks (excluding the AXI Lite clock) are at least as fast as your stream clocks.

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