2. 技术支持
  3. AR# 5489: 14.x Timing - How are the OFFSET IN and OUT constraint calculations made?
  4. AR# 54894: MIG 7 Series LPDDR2 - maximum performance has been lowered to 667 Mb/s

AR# 54894

MIG 7 Series LPDDR2 - maximum performance has been lowered to 667 Mb/s

描述

7 Series MIG IP for LPDDR2 maximum performance has been changed from original estimate of 800 Mb/s down to 667 Mb/s.

解决方案

LPDDR2 does not use a DLL to track the input clock which leads to higher variation on DQS and DQ timing. LPDDR2 MIG IP maximum performance has been set to maximum 667 Mb/s to account for the higher variation.

Revision History
03/13/13 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
45195 MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions N/A N/A
AR# 54894
日期 06/03/2013
状态 Active
Type 综合文章
器件
IP