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AR# 54897

Vivado HLS 2012 - How do you implement a global clock enable in an HLS code interface?

Description

How do you implement a global clock enable in an HLS code interface?

解决方案

For the clock enable, from the GUI select: Solution > Solution Settings > General > Add > Command: config_interface > Check the clock_enable.
This adds a port ap_ce port in your interface which acts as a clock enable.

Keep in mind that the ap_ce signal is also used as a gate signal for all outputs, which can have undesired effects in a multi-rate system in a System Generator design.

For EDK designs, this port will not be mapped on the axi4 lite control bus, but as a separate port; if the global clock gating functionality was required, the ap_start signal can be used as it will also prevent the core from running.

AR# 54897
创建日期 03/13/2013
Last Updated 06/03/2013
状态 Active
Type 综合文章
Tools
  • Vivado Design Suite - 2012.4
  • Vivado Design Suite