How to acces an active low GSR (global set/reset) for xc4000e/ex/xl or GR (global reset) for xc5200 on the STARTUP block?
Note: For xc3000 devices, the global reset signal is a dedicated pin on the device. Also, all flip-flops and latches reset to 0 after configuration.
解决方案
1
By default, GSR/GR pin are active high. To change the polarity of these signals in your VHDL or Verilog code, invert the net that sources the GSR/GR pin of the STARTUP block.
The inversion will be absorbed inside the STARTUP block; a function generator will not be used to generate the inverter. (see solution 4867 if the inverter is not absorbed inside the STARTUP block)
Since the STARTUP block doesn't have any outputs that are being used in this example, use the set_dont_touch command so that the compiler doesn't remove the STARTUP block.
set_dont_touch instance_name
See Xilinx Solution 2370 for reference to GTS in a Verilog design.
See Xilinx Solution 1670 for reference to the outputs (DONEIN, Q1Q4, Q3, Q2) on the STARTUP block.
2
XC4000e/ex/xl -- Verilog code for active low reset
module use_active_low_gsr (reset);
input reset;
// the signal reset_inv initializes all registers using the // global STARTUP signal STARTUP U0 (.GSR (~reset));
endmodule
XC4000e/ex/xl -- Run-script for compiling STARTUP Verilog Example:
PART = 4003epc84-1 TOP = use_active_low_gsr
read -format verilog TOP + ".v"
set_port_is_pad "*" insert_pads
set_dont_touch U0
compile
replace_fpga
set_attribute TOP "part" -type string PART
write -format xnf -hierarchy -output TOP + ".sxnf"
exit
3
XC4000e/ex/xl -- VHDL code for active low reset
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity use_active_low_gsr is port (reset : in STD_LOGIC); end use_active_low_gsr;
architecture xilinx of use_active_low_gsr is
component STARTUP port(GSR : in STD_LOGIC); end component;
signal reset_inv : STD_LOGIC;
begin
reset_inv <= not(reset);
-- the signal reset_inv initializes all registers using the -- global STARTUP signal U0: STARTUP port map (GSR => reset_inv);
end xilinx;
XC4000e/ex/xl -- Run-script for compiling STARTUP VHDL Example:
PART = 4003epc84-1 TOP = use_active_low_gsr
analyze -format vhdl TOP + ".vhd" elaborate TOP
set_port_is_pad "*" insert_pads
set_dont_touch U0
compile
replace_fpga
set_attribute TOP "part" -type string PART
write -format xnf -hierarchy -output TOP + ".sxnf"
exit
4
XC5200 -- VHDL code for active low reset
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity use_active_low_gr is port (reset : in STD_LOGIC); end use_active_low_gr;
architecture xilinx of use_active_low_gr is
component STARTUP port(GR : in STD_LOGIC); end component;
signal reset_inv : STD_LOGIC;
begin
reset_inv <= not(reset);
-- the signal reset_inv initializes all registers using the -- global STARTUP signal U0: STARTUP port map (GR => reset_inv);
end xilinx;
XC5200 -- Run-script for compiling STARTUP VHDL Example:
PART = 5202pc84-3 TOP = use_active_low_gr
analyze -format vhdl TOP + ".vhd" elaborate TOP
set_port_is_pad "*" insert_pads
set_dont_touch U0
compile
set_attribute TOP "part" -type string PART
write -format xnf -hierarchy -output TOP + ".sxnf"
exit
5
XC5200 -- Verilog code for active low reset
module use_active_low_gr (reset);
input reset;
// the signal reset_inv initializes all registers using the // global STARTUP signal STARTUP U0 (.GR (~reset));
endmodule
XC5200 -- Run-script for compiling STARTUP Verilog Example:
PART = 5202pc84-3 TOP = use_active_low_gr
read -format verilog TOP + ".v"
set_port_is_pad "*" insert_pads
set_dont_touch U0
compile
set_attribute TOP "part" -type string PART
write -format xnf -hierarchy -output TOP + ".sxnf"