UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54901

14.5 EDK, AXI_7series_DDRx v1.07.a - "ERROR:EDK - DDR3_ SDRAM (axi_ 7series_ ddrx) - The clock frequencies are not correct or are not correctly specified for the input clock ports..."

Description

The following error occurs when I run a DRC check for my Base System Builder MIG design:

"ERROR:EDK - DDR3_SDRAM (axi_7series_ddrx) - The clock frequencies are not correct or are not correctly specified for the input clock ports.   The specification 'Frequency of port "clk"' (133333333) * 'Parameter "C_NCK_PER_CLK"'(4)  == 'Frequency of port "mem_refclk"' (533333333) has failed."

Looking at clock frequency:
    clk = 133333333
    mem_refclk = 533333333
It is sure "mem_refclk = clk * 4".

When I set as below, I see no errors:
    clk = 125000000
    mem_refclk = 500000000

How can I work around this error? The TCL constraint cannot round properly for this use-case.

C:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_7series_ddrx_v1_07_a\data\axi_7series_ddrx_v2_1_0.tcl

 
 if {$clk_freq_mult != $mem_refclk_freq} {
   error "The clock frequencies are not correct or are not correctly specified for the input clock ports.  \
   The specification 'Frequency of port \"clk\"' ($clk_freq) * 'Parameter \"C_NCK_PER_CLK\"'($nck_per_clk) \
   == 'Frequency of port \"mem_refclk\"' ($mem_refclk_freq) ($clk_freq_mult) has failed."
 }

 

解决方案

Please change the output clock that sets the mem_refclk_freq's value, which is C_CLKOUT1_FREQ in this case.

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 533333333
 PARAMETER C_CLKOUT0_PHASE = 337.5
 PARAMETER C_CLKOUT0_GROUP = PLLE0
 PARAMETER C_CLKOUT0_BUF = FALSE
 PARAMETER C_CLKOUT1_FREQ = 533333332    <------ change this

The reason this DRC cannot catch this is it is not able to catch repeating digits.

AR# 54901
创建日期 03/13/2013
Last Updated 06/07/2013
状态 Active
Type 综合文章
Tools
  • EDK - 14.5
  • EDK - 14.4
  • EDK - 14.3
IP
  • 存储器接口发生器(MIG)