UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54907

2012.4 Vivado Synthesis - Incorrect logic is generated when converting an HDL code containing priority-mux into parallel mux as part of optimization

Description

2012.4 Vivado synthesis generates incorrect logic when attempting to convert a HDL code containing priority-mux into parallel mux as part of optimization.

Post-synthesis simulation and Onespin formal equivalency check results showed an incorrect value on a sum register. The same design worked fine in XST and Synplify.

解决方案

An issue was found in the Vivado synthesis code that performed the optimization of the following type of priority-mux structure:

if(a == b)
  out <= bdata;
else if(a == c)
  out <= cdata;
else
  out <= ddata;

The intent of the optimization was to convert the priority-mux into a parallel-mux to minimize logic levels. 

Unfortunately, this issue in version 2012.4 resulted in an incorrect logic.

To work around this issue in 2012.4, the following Tcl command needs to be used to turn off the mux optimization (before running synthesis):

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter inferMuxOpt 0"

This issue is resolved in the 2013.1 version of Vivado.

AR# 54907
创建日期 03/13/2013
Last Updated 09/02/2014
状态 Active
Type 已知问题
Tools
  • Vivado Design Suite - 2012.4