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AR# 54914

2012.4 Vivado-Simulation - Incorrect display of array aggregates of records in waveform window of XSIM

Description

When I attempt to assign an aggregate of array of records to a port, the value of this signal is not shown correctly in the waveform window. However, its value is seen correctly in the object window. Following is the part of the code in question:

type AXIS32_DAT_STRUCT is record
  TVALID : std_logic;
  TDATA  : std_logic_vector(31 downto 0); 
  TLAST  : std_logic; 
  TUSER  : std_logic_vector(3 downto 0);
end record;

type AXIS32_DAT_STRUCT_ARRAY is ARRAY (natural range <>) of AXIS32_DAT_STRUCT;

signal TEST_VECTOR: AXIS32_DAT_STRUCT_ARRAY(2 downto 0) := (
  0=>(
    TVALID=>'1',
    TDATA=>X"12345678",
    TLAST=>'1',
    TUSER=>"1111"),
  1=>(
    TVALID=>'1',
    TDATA=>X"12345678",
    TLAST=>'1',
    TUSER=>"1111"),
  2=>(
    TVALID=>'1',
    TDATA=>X"12345678",
    TLAST=>'1',
    TUSER=>"1111")
);
 
signal y: AXIS32_DAT_STRUCT_ARRAY(1 downto 0);
 
y<=TEST_VECTOR(1 downto 0);
 
FOO0: FOO PORT MAP(
  -- Input interface
  x=> TEST_VECTOR(1 downto 0)
);

end Behavioral;

The signal 'y' is also not visible in the object window. What is the reason for this?

解决方案

The signal 'y' is not used in any part of the design, hence it gets optimized during simulation. To disable this optimization, write the switch --O0 in "more compilation options" of simulation settings.

In the above code, the value of signal 'y.TDATA' is displayed correctly (i.e., X'12345678) whereas the value of 'x.TDATA' is shown incorrectly as (X'48d159e3) in the waveform window. This problem is the same with other members of record (i.e., x.TVALID,x.TLAST,x.TUSER).

The above code simulates correctly in ISIM. The screenshots of the ISIM and XSIM along with the code are attached for reference.

One work around for this in XSIM is to assign the aggregate of record array to an intermediate signal, then connect this signal to the formal port as shown below:

y <= TEST_VECTOR(1 downto 0);

FOO0: FOO PORT MAP(
  x => y 
);

end Behavioral;

Attachments

文件名 文件大小 File Type
chFPGA.vhd 2 KB VHD
XSIM_record.png 72 KB PNG
ISIM_record_corectdisplay.png 137 KB PNG
AR# 54914
创建日期 03/14/2013
Last Updated 05/31/2013
状态 Active
Type 综合文章
器件
  • FPGA Device Families
Tools
  • Vivado - 2012.4