描述

解决方案

This is expected behavior.  When entering or exiting Far-end PMA Loopback mode, the switching of the clock domains may cause a glitch, which in turn can cause clock dividers (TXPLL_DIVSEL_OUT) internal to the GTX to lock up.  When this occurs, the observation is that TXOUTCLK will be flatlined if TXOUTCLK_CTRL is not equal to TXPLLREFCLK_DIV1 or TXPLLREFCLK_DIV2. Once the clock flatlines, GTXTEST[1] or GTXTXRESET will need to be toggled to recover the clock.

So, the correct use model for Far-end PMA loopback should be as follows:
- When switching into Far-end PMA Loopback mode, user should toggle GTXTEST[1] or GTXTXRESET before expecting correct operation.
- When switching out of Far-end PMA Loopback mode, user should also toggle GTXTEST[1] or GTXTXRESET before expecting correct operation.

Refer to Figure 3-19 in Virtex-6 FPGA GTX Transceivers User Guide (UG366) for the GTXTEST[1] toggling diagram.
Refer to Figure 3-11 in Virtex-6 FPGA GTX Transceivers User Guide (UG366) for the GTXTXRESET toggling diagram.