I am using the AXI VDMA in my design and I am seeing one or more of the following behaviors:
Why is there throttling? Why are there errors? Why is tkeep acting strange? Do I need to drive s2mm_tkeep the same?
Though it should first be noted that these behaviors may be indicative of other issues, one possible solution may be to enable the Data Realignment Engine (DRE) by checking the 'Allow Unaligned Transfers' option when configuring the core.
This behavior may be caused by a some type of mis-alignment, possibly indicating an issue with the tdata width, hsize, and/or stride settings. As per the product guide, when C_INCLUDE_S2MM_DRE = 0, then the Start Address must be aligned to multiples of C_M_AXI_S2MM_DATA_WIDTH bytes. Also Horizontal Size and Stride must be specified in even multiples of C_M_AXI_S2MM_DATA_WIDTH bytes.
However, by enabling the DRE, these restrictions are no longer applicable and the user is allowed to use un-aligned values because the core will handle re-alignment for you automatically (at the cost of increased area footprint due to extra logic). Do note that the DRE is only supported for AXI Stream Data widths settings of 64 bits or less.
One common application where such a mis-alignment may unexpectedly occur is when scaling the frame size. If an application requires arbitrarily sized frames to be transferred to memory, it is very likely that a mis-alignment will occur at some point because the AXI VDMA's Horizontal Size must be adjusted at run-time to compensate. Thus, in many cases (i.e. for many scale factors), the Horizontal Size may no longer be an even multiple of C_M_AXI_S2MM_DATA_WIDTH.
Therefore, we recommend enabling the Data Realignment Engine in the AXI VDMA when used with the Video Scaler core.
For a detailed list of LogiCORE IP AXI Video Direct Memory Access Release Notes and Known Issues, see (Xilinx Answer 47654).