When changing the Spartan-6 FPGA FIFO model timescale directives, the outputs of the model begin to contain glitches. Is this expected?
The timescale directives of the simulation models are set to reflect the optimal simulation performance while maintaining the proper functional operation of the model. These directives should not be changed, as they can cause improper operation of the model. This is a simulation only issue, and does not affect the hardware operation of the design.