UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54941

Zynq-7000 AP SoC Example, EDK 14.3 - Using axi_dma to move axi-stream data to/from the PL from/to DDR in the PS via the HP0 Port

Description

Raw data often needs to be moved between the PL and the PS. 

By formatting the raw data into an AXI-Stream interface, the axi_dma core can be used to convert the streaming data to AXI4 data.

Either the PS DDR or PS OCM can be targeted by changing the destination/source address written to the DMA controller.

 

解决方案

This design contains a simple axi-stream generator/terminator which is connected to the streaming interfaces on the axi_DMA core. 

The DMA has been configured as simple DMA so no descriptors are required. 

The AXI4 master interfaces of the axi_dma have been connected to the HP0 port of the PS.

This connection could be easily changed to the PS ACP port. 

If the design is changed to the ACP port, make sure that the option 'Use slave driven AxUSER values' is not checked in the ACP configuration window. 

This way, the PS wrapper will drive the AxUSER and AxCACHE signals appropriately to enable cache coherency.


The example software has been written to simply move one packet of data in each direction between the generator and DDR.


ChipScope is used to monitor the axi-stream and axi4 interfaces and the ChipScope VIO core is used to control the generator enable and to control the flow-control signals on the axi_dma master AXI-Stream interface.

 

A complete design is attached to this article. 


The readme file describes creating and using the design.

Attachments

文件名 文件大小 File Type
axi_dma-54941.zip 1 MB ZIP
AR# 54941
创建日期 03/15/2013
Last Updated 03/05/2015
状态 Active
Type 综合文章
器件
  • Zynq-7000
Tools
  • EDK - 14.3
IP
  • AXI DMA Controller