Version Found: v1.8
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)
When 4 byte groups are used for address and control signals MIG assigns the incorrect vector size to the ADDR_CTL_MAP in the top level files. Only a 24-bit vector is used when 32 bits are required.
The vector size is set up to only handle spreading address and control across 3 byte lanes but 4 is also acceptable.
To work around this issue, the width of the ADDR_CTL_MAP parameter needs to be increased to 32-bits and updated to match your byte and bit position within the top-level of your design (refer to UG586 for ADDR_CTL_MAP description):
parameter ADDR_CTL_MAP = 32'h00_00_12_13,
Note: This will only affect designs using a "Fixed Pin Out" as the Bank Selection page limits all address and control I/O into only 2 byte groups within the same bank.
04/03/2013 - Initial release