AR# 55038

LogiCORE 10-Gigabit Ethernet MAC v12.0 - VHDL - Internal XGMII interface; tx_dcm_locked port not driven in example design

描述

In the 10-Gigabit Ethernet MAC v12.0 Internal XGMII interface VHDL example design, the tx_dcm_locked input to the physical interface block is not driven. 

This results in the example design simulation not completing.

解决方案

To work around this issue, change the tx_dcm_locked input for ten_gig_eth_mac_0_physical_if in the core_name_example_design.vhd file.

from

tx_dcm_locked => tx_dcm_locked_reg,

to

tx_dcm_locked => tx_dcm_locked,

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54252 LogiCORE IP 10G Ethernet MAC - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 55038
日期 09/22/2014
状态 Active
Type 已知问题
IP