AR# 55129

MIG 7 Series QDRII+ - Cypress memory model fails simulation for designs with Burst Length(BL) = 2 and Data Width = 18

描述

Version Found: v1.5
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)

Cypress memory models fail simulation with watch dog timer errors during calibration for MIG QDRII+ designs with BL=2 and DATA_WIDTH=18.

解决方案

This is a known issue with the Cypress BL2 memory model and can be worked around by making the following changes in the CY7C25442KV18.v model:

Change:

always @(posedge IoutClk)
  begin
    if (rpen_o_o == 0)
      chip_oe = `tchz 1;
    else
      chip_oe = `tchz 0;
  end

To:

always @(posedge IoutClk)
  begin
    if (rpen_o == 0)
      chip_oe = `tchz 1;
    else
      chip_oe = `tchz 0;
  end

Revision History
04/03/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 55129
日期 10/15/2014
状态 Active
Type 已知问题
器件
IP