AR# 55132


LogiCORE XAUI v11.0 - Vivado - Artix-7 - 20G DXAUI - Marginal timing seen


When using v11.0 XAUI core configured for 20G DXAUI, marginal timing has been seen when targeting Artix-7 devices. 


When small timing failures are seen, changing Vivado Synthesis and Implementation tool options have been seen to result in passing timing.  Some possibilities include:

  • In Implementation Settings under Place Design, set the directive to ExtraPostPlacementOpt.
  • In Synthesis Settings, change control_set_opt_threshold to 60.



Answer Number 问答标题 问题版本 已解决问题的版本
54666 LogiCORE IP XAUI - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 55132
日期 06/10/2013
状态 Active
Type 综合文章
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