AR# 55136

MIG 7 Series RLDRAM II - timing violation found for "u_phy_write_init_sm/rst_clk_sync_r" path

描述

Version Found: v1.9
Version Resolved: See (Xilinx Answer 45195)
 
Timing failures might occur on the "u_phy_write_init_sm/rst_clk_sync_r" path for RLDRAM II designs.
 
Timing failure example:
Slack (setup path):     -0.021ns (requirement - (data path - clock path skew + uncertainty))
  Source:                      u_mig_7series_v1_9/u_rld_memc_ui_top_std/u_rld_phy_top/u_phy_write_top/u_phy_write_init_sm/rst_clk_sync_r_4_1 (FF)
  Destination:               u_mig_7series_v1_9/u_rld_memc_ui_top_std/gen_ui_fifos.u_rld_ui_top/u_usr_addr_fifo/u_af/FIFO36E1 (RAM)
  Requirement:            4.444ns
  Data Path Delay:      4.274ns (Levels of Logic = 0)

解决方案

These timing failures only occur when using ISE and do not affect Vivado.

To work around the timing violations, the following code must be modified:

In the file mig_7series_v1_9_rld_phy_write_init_sm.v:
 
Replace:

  (* max_fanout = "50" *)
  reg [RST_SYNC_NUM-1:0]  rst_clk_sync_r     = -1;

with:

  reg [RST_SYNC_NUM-2:0]  rst_clk_sync_r     = -1;
  (* max_fanout = "50" *)
  reg rst_clk_sync_r1     ;

Replace:

  always @(posedge clk)
    if (rst_wr_clk || !cnt_pwron_reset_done_r)
      rst_clk_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
    else
      rst_clk_sync_r <= #TCQ rst_clk_sync_r << 1;
  
  assign rst_clk = rst_clk_sync_r[RST_SYNC_NUM-1];

with:

  always @(posedge clk) begin
    if (rst_wr_clk || !cnt_pwron_reset_done_r) begin
      rst_clk_sync_r <= #TCQ {RST_SYNC_NUM-1{1'b1}};
      rst_clk_sync_r1 <= #TCQ 1'b1;
    end else begin
      rst_clk_sync_r <= #TCQ rst_clk_sync_r << 1;
      rst_clk_sync_r1 <= #TCQ rst_clk_sync_r [RST_SYNC_NUM-2];
    end
  end

  assign rst_clk = rst_clk_sync_r1;

Revision History
04/03/2013 - Initial Release
AR# 55136
日期 01/26/2015
状态 Active
Type 已知问题
器件
IP