AR# 55146


MIG 7 Series RLDRAM II - timing error due to high net delay in Vivado implementation


Version Found: v1.9
Version Resolved: See (Xilinx Answer 54025)

When implementing the MIG 7 Series RLDRAM II design, the following timing violations might be seen:

Slack (VIOLATED) :        -0.410ns
  Source:                 u_mig_7series_v1_9_a_0/u_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_0.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_A.qdr_rld_byte_lane_A/out_fifo_inst.out_fifo/WRCLK
                            (rising edge-triggered cell OUT_FIFO clocked by clk_pll_i  {rise@0.000ns fall@2.222ns period=4.444ns})
  Destination:            u_mig_7series_v1_9_a_0/u_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_0.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_A.qdr_rld_byte_lane_A/GEN_PRE_FIFO.u_qdr_rld_pre_fifo/my_empty_reg[3]_rep__13_rep__0_rep__0_rep/D
                            (rising edge-triggered cell FDSE clocked by clk_pll_i  {rise@0.000ns fall@2.222ns period=4.444ns})
  Path Group:             clk_pll_i
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.444ns
  Data Path Delay:        4.542ns  (logic 0.359ns (7.903%)  route 4.183ns (92.097%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.262ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.973ns = ( 7.417 - 4.444 ) 
    Source Clock Delay      (SCD):    3.300ns
    Clock Pessimism Removal (CPR):    0.065ns
  Clock Uncertainty:      0.050ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.070ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         net (fo=1757, routed)        4.183     7.875    u_mig_7series_v1_9_a_0/u_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_0.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_A.qdr_rld_byte_lane_A/GEN_PRE_FIFO.u_qdr_rld_pre_fifo/I1


This timing violation is a result of high fan out on the delay path.

Please open a webcase with Xilinx Technical support if assistance is needed.

Revision History
04/03/2013 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 55146
日期 01/26/2015
状态 Active
Type 已知问题
People Also Viewed