AR# 55243


LogiCORE IP FIR Compiler v7.0 - Core is incorrectly synthesized when core configure with dynamic shift ram inference


If I synthesize the core within Vivado Design Suite 2013.1 with FIR Compiler v7.0, the block that implements a dynamic shift RAM is not being synthesized correctly.


This is a known issue with FIR Compiler v7.0. The error is confined to the following FIR Compiler configurations of the core:

  • Advanced Channel Configuration and with a single pattern is specified
  • A single channel within the pattern appears in adjacent slots (e.g., 0001 or 00000012).

The error will show up in any netlist simulation and in hardware as a persistent mismatch of M_AXIS_DATA_TDATA versus the desired behavior (as described by the simulation model).

To work around this issue, specify a second pattern where no channel appears in consecutive slots (e.g., 0101 or 01230123). This second pattern need not be used.



Answer Number 问答标题 问题版本 已解决问题的版本
54502 IP Release Notes and Known Issues for LogiCORE IP FIR Compiler core for Vivado 2013.1 and newer tools N/A N/A
AR# 55243
日期 06/11/2013
状态 Active
Type 综合文章
器件 More Less
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