AR# 55245

Design Assistant for Vivado Synthesis - XDC Synthesis Attributes Support; SHREG_EXTRACT, ROM_STYLE, RAM_STYLE, MAX_FANOUT

描述

This answer record shows the support of some of the Vivado synthesis properties in XDC:

SHREG_EXTRACT, ROM_STYLE, RAM_STYLE, MAX_FANOUT

Example codes and constraints are attached at the end of this answer record.

解决方案

Support for these properties:


SHREG_EXTRACT:

This property instructs the synthesis tool to infer shift registers.

Example: set_property SHREG_EXTRACT NO [get_cells shreg_reg*]

This property works in the current version of the tool and can be set via XDC.


ROM_STYLE:

This property instructs the synthesis tool to infer a ROM memory.

Example: set_property ROM_STYLE BLOCK [get_cells do0_1]

This property works in the current version of the tool and can be set via XDC.


RAM_STYLE:

This property instructs the synthesis tool to infer RAM memory.

Example:  set_property RAM_STYLE DISTRIBUTED [get_cells hier mem_reg*]

This property works in the current version of the tool and can be set via XDC.


MAX_FANOUT:

This property instructs the synthesis tool on the fanout limits for registers and signals.

Example:  set_property MAX_FANOUT 10 [get_nets ena]

This property is working in the current version of tool.

For example, "report_property [get_nets count[31\\\]]" will report that the MAX_FANOUT attribute was set to 10 in the synthesized netlist.



Codes and Constraints examples:


Table 1-1

Coding example name Property

shreg_extract.zip

  • shreg_extract

rom_style.xpr.zip

  • rom_style

ram_style.xpr.zip

  • ram_style
max_fanout.zip
  • max_fanout

 

附件

文件名 文件大小 File Type
shreg_extract.zip 36 KB ZIP
max_fanout.zip 656 Bytes ZIP
ram_style.xpr.zip 9 KB ZIP
rom_style.xpr.zip 9 KB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
55260 Design Assistant for Vivado Synthesis - XDC Synthesis Attributes and Timing Constraints Support N/A N/A
AR# 55245
日期 12/02/2014
状态 Active
Type 解决方案中心
Tools