This answer record describes how the Synthesis tool processes some XDC timing constraints:
create_clock
set_multicycle_path
set_input_delay
set_output_delay
set_false_path
Support for these properties
It is advised to have timing constraints in the XDC during Synthesis because the Synthesis tool, being timing-driven, uses these constraints as guides when doing optimization.
At the moment, the Synthesis report does NOT mention the timing constraints that are processed by the Synthesis tool.
As a result, you will have to open the synthesized netlist and query for them (for example, using report_timing) to confirm that the constraints were applied.
create_clock
This XDC command is used to create a clock and It is the main timing constraint in any design.
Using the get_clock command with the opened Synthesized netlist will return the list of clocks and you can confirm if the clock was created during synthesis.
set_input_delay
This XDC command is used to constrain the input paths.
Use report_timing to get a report of the path and to confirm if the input delay was applied correctly.
The input delay will be listed and the value can also be confirmed.
For Example:
report_timing -from [get_ports datain2]
set_output_delay
This XDC command is used to constrain the output paths.
Use report_timing to get a report of the path and confirm if the output delay was applied correctly.
The output delay will be listed and the value can also be confirmed.
For Example:
report_timing -to [get_ports dataout]
set_false_path
This XDC command is used to disable timing paths.
Use report_timing to confirm that the slack is 'inf' to confirm that it was applied.
For Example:
report_timing -from [get_cells data3_reg] -to [get_cells data4_reg]
set_multicycle_path
This XDC command is used to set multicyle paths.
Use report_timing to confirm that the requirement is set to the requested multiplication factor.
For Example:
report_timing -from [get_cells data2_reg] -to [get_cells data3_reg]
Example code for the Timing Constraints
The attached timing_constraints.zip file contains an example code that demonstrates processing timing constraints during synthesis.
文件名 | 文件大小 | File Type |
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timing_constraints.zip | 1019 Bytes | ZIP |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
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55260 | Design Assistant for Vivado Synthesis - XDC Synthesis Attributes and Timing Constraints Support | N/A | N/A |
AR# 55254 | |
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日期 | 03/24/2015 |
状态 | Active |
Type | 解决方案中心 |
Tools |