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AR# 55287

Vivado Constraints - Using Virtual Clocks to constrain input to output feed-through paths


How can I set the input and output delays to constrain the pure combinatorial pad to pad paths?


You can take advantage of virtual clocks, which represent the clock at the external device connected to the FPGA, to constrain this type of path.

A basic XDC constraint for this type of set-up is shown below:


# Create virtual clocks 

create_clock -period 10 -name virtclk

# Set input and output delay

set_input_delay -clock [get_clocks virtclk] -max <input_delay_value> [get_ports padin]

set_output_delay -clock [get_clocks virtclk] -max <output_delay_value> [get_ports padout]

#where input_delay_value + maximum feedthrough path delay + output_delay_value = virtclk period


For more information on constraining the input to output feed-through paths (pad to pad paths), please refer to UG949 - "UltraFast Design Methodology Guide for the Vivado Design Suite".

AR# 55287
日期 12/16/2014
状态 Active
Type 综合文章
  • Vivado Design Suite