AR# 55339


LogiCORE IP Serial RapidIO Gen2 v1.7 - Release Notes and Known Issues for ISE Design Suite 14.5


This Release Note and Known Issues Answer Record is for the LogiCORE IP Serial RapidIO Gen2 v1.7 which was released in the ISE 14.5 design tool and contains the following information:
  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues
  • Other Information
For installation instructions, general CORE Generator tool known issues, and design tool requirements, see the IP Release Notes Guide.


New Features
    • ISE 14.5 design tools support
Supported Devices
The following device families are supported by the core for this release:
  • Virtex-7 devices:
    • Virtex-7
    • Virtex-7 -2G
    • Virtex-7 XT
    • Virtex-7 Low Voltage (-2L)
  • Kintex-7 devices:
    • Kintex-7
    • Kintex-7 Low Voltage (-2L)
  • Artix-7 devices:
    • Artix-7
    • Artix-7 Lower Power (-2L)
  • Virtex-6 devices:
    • Virtex-6 CXT/LXT/SXT/HXT
    • Virtex-6 Lower Power (-1L) LXT/SXT
Resolved Issues
Known Issues
    • When the ChipScope tool is enabled for the example design, timing might not be met during the implementation process
    • (Xilinx Answer 50883) - Implementation might fail with slack violation timing error
    • (Xilinx Answer 53542) - Link might train down on 6.25Gbaud x2 and 6.25Gbaud x4 core configurations
    • (Xilinx Answer 54372) - Support for devices with GTH
    • (Xilinx Answer 55344) - Certain configurations may not fit into the number of slices available
    • (Xilinx Answer 55153) - Core generated for Artix-7 production device fails in behavioral simulation with "ERROR: TEST FAILED" message
    • (Xilinx Answer 55724) - Data following truncated clock compensation sequence not descrambled correctly in IDLE2
Other Information
Revision History
04/03/2013 - Initial release
04/29/2013 - Added (Xilinx Answer 55724) and (Xilinx Answer 55736).



AR# 55339
日期 05/02/2013
状态 Active
Type 版本说明
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