AR# 55351


AXI Bridge for PCI Express v1.06.a - Missing completion for Memory Read when configured as RC x4Gen2 on Zynq devices


Version Found: v1.06.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When the AXI Bridge for PCI Express v1.06.a core is configured as x4Gen2 Root Complex for a Zynq device, the core does not send the corresponding CplD TLP in response to the read from the endpoint.


This is a known issue and will be fixed in the next release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. 该问题可能也出现于较早版本,但未对较早版本进行特定测试。




Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 55351
日期 07/10/2013
状态 Active
Type 已知问题
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