Version Found: v1.06.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)
When the AXI Bridge for PCI Express v1.06.a core is configured as x4Gen2 Root Complex for a Zynq device, the core does not send the corresponding CplD TLP in response to the read from the endpoint.
This is a known issue and will be fixed in the next release of the core.
Note: "Version Found" refers to the version where the problem was first discovered. 该问题可能也出现于较早版本，但未对较早版本进行特定测试。