If using the MDIO interface and targeting a 7 series device with a GTX transceiver when using the Ten Gigabit Ethernet PCS/PMA v3.0 and earlier, activity on MDIO Interface or MDIO registers could be corrupted if 3.42.5 RX PRBS31 pattern checking is enabled. This bit should not be enabled via the MDIO interface.
If using a 7 series GTH transceiver, see (Xilinx Answer 55728).
The RX PRBS31 pattern checking is done in the GTX transceiver and the error count is read from the GT DRP registers via the DRP interface. If using RX PRBS31 pattern checking, this issue can be worked around by:
1) Using the configuration vector and status vector instead of the MDIO interface
2) Using the Training Interface available for 10GBASE-KR
The following sequence can be used if using the training interface:
a. Write to ipif address x03002A to set PRBS31 TX and RX bits (bits 4 and 5) (reg3.42)
This will set the correct pins on the GT.
b. Optionally, enable PMA Loopback with ipif reg x010000, bit 0. If you do not enable loopback, you will see errors (unless the RX is driven by another core which is transmitting PRBS31)
c. Read from GTX DRP RX_PRBS_ERR_CNT register. For GTX transceivers the address for this counter is 0x15C. When errors are being logged, the number being read will steadily increase.
d. To clear the counter at any time, read from ipif address x03002B and ignore the result. (3.43)
This will automatically toggle the RXPRBSCNTRESET pin on the GT.
e. Write to ipif reg x03002A to turn off PRBS31 TX/RX.
3) Directly access the GT DRP to read the RX PRBS error count, and directly set the GT RX/TXPRBSSEL and RXPRBSCNTRESET
If 10G BASE-R is used, the DRP interface to the GT can be disconnected from the core to allow user to directly connect to DRP interface on the GT, since the 10GBASE-R core is only connected to the GT DRP interface to read RX PRBS31 error count.
If 10G BASE-KR is used, some arbitration logic may need to be used since the Training Interface enables access to additional GT DRP registers.