描述

解决方案

You can use the following command for both project-mode and non-project mode to modify the device configuration settings:

set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]

• If the top file of non-project design is RTL code(system verilog/verilog/VHDL), the set_property command could be used after synth_deisgn command

  Example: 
  
  read_vhdl -library bftLib [ glob ./Sources/hdl/bftLib/*.vhdl ]
  read_vhdl ./Sources/hdl/bft.vhdl
  read_verilog [ glob ./Sources/hdl/*.v ]
  read_xdc ./Sources/bft_full.xdc
  synth_design -top bft -part xc7k70tfbg484-2 -flatten rebuilt 
  set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]
  opt_design
  power_opt_design 
  place_design
  phys_opt_design 
  route_design
  write_bitstream -force ./bft.bit

• If the top file of non-project design is the netlist file(ngc/edf), the set_property command could be used after link_deisgn command

  Example: 
  
  set_property design_mode GateLvl [current_fileset]
  set_property part xc7k70tfbg484-2 [current_project]
  set_property edif_top_file ./Sources/top.edf [current_fileset]
  read_edif [glob ./Sources/top.edf]
  read_xdc ./Sources/bft_full.xdc
  link_design 
  set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]
  opt_design
  power_opt_design 
  place_design
  phys_opt_design 
  route_design
  write_bitstream -force bft.bit