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AR# 55707

14.5 EDK, Zynq-7000 - FSBL unable to boot when using 32-bit HP AXI ports


When using the HP AXI ports at a 32-bit width in 7045ES and production Zynq devices, the FSBL is unable to boot and the CPU appears to be hung, with no access from JTAG. 我该如何解决此问题?


In 7045ES and production Zynq devices, the bootROM no longer clears the required reserved bits in the FPGA_RST_REG register. When these reserved bits are '1', the HP/AFI registers cannot be accessed, causing a CPU hang. In the AXI HP 64-bit mode setting, the ps7_init function does not access the register.

This issue is planned to be fixed in the Xilinx FSBL starting in 14.6/2013.2.

To work around the issue, add the following code to the FSBL, above the function call of ps7_init():

Note: This workaround can be removed in version 14.6/2013.2 and later.

#define FPGA_RESET_MASK 0xf SlcrUnlock(); Xil_Out32(FPGA_RESET_REG, FPGA_RESET_MASK); /*clear required 0 bits, leave FPGA resets active */ SlcrLock();
AR# 55707
日期 06/07/2013
状态 Active
Type 综合文章
  • Zynq-7000
  • Zynq-7000Q
  • XA Zynq-7000
  • Vivado Design Suite - 2013.1
  • EDK - 14
  • EDK - 14.5
  • Processing System 7