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AR# 55724

LogiCORE IP Serial RapidIO Gen2 v1.7/v2.0 - Data following truncated clock compensation sequence not descrambled correctly in IDLE2

描述

Version Found: 1.7 / 2.0
Version Resolved and other Known Issues: See (Xilinx Answer 55339) for v1.7, and (Xilinx Answer 54648) for v2.0

If IDLE2 is used, truncated clock compensation sequence can cause an unexpected PNA to be sent by the core due to data following the truncated clock compensation sequence not being descrambled correctly.

解决方案

This is a known issue to be fixed in the next release of the core.

For the fix in v1.7 of the core, install Rev1 patch for this core available in (Xilinx Answer 55736).

For the v2.0 core, install Rev1 patch available in (Xilinx Answer 55737).

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/02/2013 - Initial release

链接问答记录

主要问答记录

AR# 55724
日期 11/05/2013
状态 Active
Type 综合文章
IP
  • Serial RapidIO
的页面