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AR# 5576

M1.5i - Ngdbuild : ERROR:basnu:192 - The LUT2_L symbol ... does not have any programming information

Description

Keywords: Virtex, basnu:192, LUT2_L, INIT, ngdbuild, synopsys

Urgency: Standard

General Description:
When implementing a Virtex design synthesized by Synopsys FPGA/Design Compiler, The following error may occur in ngdbuild:

ERROR:basnu:192 - The LUT2_L symbol "I_HDSL_TX/I_HDSL_TX_SP1/I_TX_GEN/add_4323/add_4323/A_LUT_13" does not have any programming information. The behavior of a LUT2_L symbol must be defined by an INIT property or an EQN property.

This message means that the symbol (LUT2_L) that was inferred in the netlist does not have some of the program information that is defined using the INIT and EQN attributes.

Synopsys synthesis tool is not writing those attributes into the netlist.

解决方案

1

Export your netlist in an SEDIF format <design.sedif>. You should not write out XNF or EDIF netlist formats.

In FPGA/Design compiler synthesis script use the following command:

write -format edif -hierarchy -output TOP + ".sedif"


See (Xilinx Solution 5048) for more caveats about compiling HDL for Virtex designs using Synopsys compilers.

2

Make sure that you are using the .synopsys_dc.setup file specifically designed for Virtex devices. This file can be found at:

$XILINX/synopsys/example/template.synopsys_dc.setup_virtex

Synopsys directives are used to specify the type of information to be exported to the netlist. These synthesis directives are defined in your Synopsys initialization file (.synopsys_dc.setup). For example:

edifout_write_properties_list = {"INIT" "EQN"}

3

Do not use "uniquify" or "ungroup" in your run script. This is a known issue with uniquify, for more info, see (Xilinx Solution 5048).
AR# 5576
创建日期 02/02/1999
Last Updated 06/13/2002
状态 Archive
Type 综合文章